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RISS 인기검색어
- 검색키워드
- 저자 : Duong Huynh-Thai Vo (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
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Jong-Wook Lee,Duong Huynh Thai Vo,Quoc-Hung Huynh,Sang Hoon Hong IEEE 2011 IEEE transactions on industrial electronics Vol.58 No.6
<P>We present a fully integrated small-size HF-band passive RF identification (RFID) tag chip with authentication and security functions. The design of the RF transceiver and digital control of the tag IC is based on the International Organization for Standardization-14443 type-B protocol. The design of the key analog part of the tag IC is presented, which includes a robust demodulator for 10% amplitude shift keying envelope detection, a high-quality random number generator, and a voltage regulator that can handle a range of output load currents. To implement the secure data transaction with a reader, a 128-b advanced encryption standard (AES) with a new cyclic key generation is used for the data encryption and decryption. An on-chip 4-kb electrically erasable programmable ROM (EEPROM) is used to support the AES operation, tag identification, and tag self-destruction. The read and write accesses of the EEPROM are performed using a 128-b wide buffer with self-timed bursts. The tag chip is fabricated in a one-poly six-metal low-power 0.18-μm CMOS process with a CoSi<SUB>2</SUB> Schottky diode and EEPROM process. Using the scaled-down CMOS technology, the size of the tag chip is only 1.1 × 1 mm<SUP>2</SUP>, providing a cost-effective solution for everyday RFID applications.</P>
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A Fully Integrated EPC Gen-2 UHF-Band Passive Tag IC Using an Efficient Power Management Technique
Jong-Wook Lee,Ngoc Dang Phan,Duong Huynh-Thai Vo,Vinh-Hao Duong IEEE 2014 IEEE transactions on industrial electronics Vol.61 No.6
<P>We present a system-on-chip passive tag integrated circuit (IC) for secure near-field RF identification applications. The design of the RF transceiver and the digital control of the tag IC are based on the EPCglobal ultrahigh-frequency Gen-2 protocol. A new design technique for the power management of the tag IC is presented, which includes a low-voltage bandgap, a low-dropout regulator with a bias-boosted gain stage, and an adaptive dc limiter. With the proposed design technique, we achieve a high power conversion efficiency of 47% at a low input power of -12 dBm. To support data security, we use one-time programmable (OTP) memory for nonvolatile data storage. The 4-kb (256 × 16 b) OTP memory array is based on a two-transistor (2-T) gate-oxide antifuse that can be programmed with a voltage of less than 6 V. The tag chip was fabricated in a 1-poly 6-metal standard 0.13- μm CMOS process. The power consumption levels of the tag IC are 29.2 and 71.2 μW for the read and programming modes, respectively. The size of the tag chip is 1.1×1 mm<SUP>2</SUP>.</P>
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