An FPGA-Based Modified Adaptive PID Controller for DC/DC Buck Converters

Lv, Ling,Chang, Changyuan,Zhou, Zhiqi,Yuan, Yubo The Korean Institute of Power Electronics 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.2

On the basis of the conventional PID control algorithm, a modified adaptive PID (MA-PID) control algorithm is presented to improve the steady-state and dynamic performance of closed-loop systems. The proposed method has a straightforward structure without excessively increasing the complexity and cost. It can adaptively adjust the values of the control parameters ($K_p$, $K_i$ and $K_d$) by following a new control law. Simulation results show that the line transient response of the MA-PID is better than that of the adaptive digital PID because the differential coefficient $K_d$ is introduced to changes. In addition, experimental results based on a FPGA indicate that the MA-PID control algorithm reduces the recovery time by 62.5% in response to a 1V line transient, 50% in response to a 500mA load transient, and 23.6% in response to a steady-state deviation, when compared with the conventional PID control algorithm.

An FPGA-Based Modified Adaptive PID Controller for DC/DC Buck Converters

Ling Lv,Changyuan Chang,Zhiqi Zhou,Yubo Yuan 전력전자학회 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.2

On the basis of the conventional PID control algorithm, a modified adaptive PID (MA-PID) control algorithm is presented to improve the steady-state and dynamic performance of closed-loop systems. The proposed method has a straightforward structure without excessively increasing the complexity and cost. It can adaptively adjust the values of the control parameters (Kp, Ki and Kd) by following a new control law. Simulation results show that the line transient response of the MA-PID is better than that of the adaptive digital PID because the differential coefficient Kd is introduced to changes. In addition, experimental results based on a FPGA indicate that the MA-PID control algorithm reduces the recovery time by 62.5% in response to a 1V line transient, 50% in response to a 500mA load transient, and 23.6% in response to a steady-state deviation, when compared with the conventional PID control algorithm.

Rapid Dynamic Response Flyback AC-DC Converter Design

Changyuan Chang,Menglin Wu,Luyang He,Dadi Zhao 전력전자학회 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.6

A constant voltage AC-DC converter based on digital assistant technology is proposed in this paper, which has rapid dynamic response capability. The converter operates in the PFM (Pulse Frequency Modulation) mode. According to the load state, the compensation current produced by the digital compensation module was injected into the CS pin to adjust the switching pulse width dynamically and improve the dynamic response. The control chip is implemented based on NEC 1μm 5V/40V HVCMOS process. A 5V/1.2A prototype has been built to verify the proposed control method. When the load jumps from idle to heavy, the undershoot time is only 7.4ms.

Design of a High-Precision Constant Current AC-DC Converter with Inductance Compensation

Changyuan Chang,Yang Xu,Bin Bian,Yao Chen,Junjie Hu 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.3

A primary-side regulation AC-DC converter operating in the PFM (Pulse Frequency Modulation) mode with a high precision output current is designed, which applies a novel inductance compensation technique to improve the precision of the output current, which reduces the bad impact of the large tolerance of the transformer primary side inductance in the same batch. In this paper, the output current is regulated by the OSC charging current, which is controlled by a CC (constant current) controller. Meanwhile, for different primary inductors, the inductance compensation module adjusts the OSC charging current finely to improve the accuracy of the output current. The operation principle and design of the CC controller and the inductance compensation module are analyzed and illustrated herein. The control chip is implemented based on a TSMC 0.35μm 5V/40V BCD process, and a 12V/1.1A prototype has been built to verify the proposed control method. The deviation of the output current is within ±3% and the variation of the output current is less than 1% when the inductances of the primary windings vary by 10%.

An Analysis of the Limit Cycle Oscillation in Digital PID Controlled DC-DC Converters

Changyuan Chang,Chao Hong,Xin Zhao,Cheng`en Wu 전력전자학회 2017 JOURNAL OF POWER ELECTRONICS Vol.17 No.3

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.

Flyback AC-DC Converter with Low THD Based on Primary-Side Control

Changyuan Chang,Luyang He,Zixuan Cao,Dadi Zhao 전력전자학회 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.6

A single-stage flyback LED AC-DC converter based on primary-side control under constant current mode is proposed in this study. The proposed converter features low total harmonic distortion (THD) and high power factor (PF). It also consists of a zero-crossing distortion compensation circuit and a variable duty ratio control compensation circuit to deal with the line current distortions caused by fixed duty ratio control. The system model and layout are built in Simplis and Cadence, respectively. The feasibility and performance of the proposed circuit is verified by designing and fabricating an IC controller in the HHNEC 0.35 μm 5 V/40 V HVCMOS process. Experimental results show that the PF can reach a level in the range of 0.985–0.9965. Moreover, the average THD of the entire system is approximately 10%, with the minimum being 6.305%, as the input line voltage changes from 85 VAC to 265 VAC.

Analysis and Design of a Separate Sampling Adaptive PID Algorithm for Digital DC-DC Converters

Changyuan Chang,Xin Zhao,Chunxue Xu,Yuanye Li,Cheng`en Wu 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.6

Based on the conventional PID algorithm and the adaptive PID (AD-PID) algorithm, a separate sampling adaptive PID (SSA-PID) algorithm is proposed to improve the transient response of digitally controlled DC-DC converters. The SSA-PID algorithm, which can be divided into an oversampled adaptive P (AD-P) control and an adaptive ID (AD-ID) control, adopts a higher sampling frequency for AD-P control and a conventional sampling frequency for AD-ID control. In addition, it can also adaptively adjust the PID parameters (i.e. Kp, Ki and Kd) based on the system state. Simulation results show that the proposed algorithm has better line transient and load transient responses than the conventional PID and AD-PID algorithms. Compared with the conventional PID and AD-PID algorithms, the experimental results based on a FPGA indicate that the recovery time of the SSA-PID algorithm is reduced by 80% and 67% separately, and that overshoot is decreased by 33% and 12% for a 700㎃ load step. Moreover, the SSA-PID algorithm can achieve zero overshoot during startup.

An Analysis of the Limit Cycle Oscillation in Digital PID Controlled DC-DC Converters

Chang, Changyuan,Hong, Chao,Zhao, Xin,Wu, Cheng'en The Korean Institute of Power Electronics 2017 JOURNAL OF POWER ELECTRONICS Vol.17 No.3

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.

A Novel Zero-Crossing Compensation Scheme for Fixed Off-Time Controlled High Power Factor AC-DC LED Drivers

Changyuan Chang,Hailong Sun,Wenwen Zhu,Yao Chen,Chenhao Wang 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.5

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5㎛ 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

Rapid Dynamic Response Flyback AC-DC Converter Design

Chang, Changyuan,Wu, Menglin,He, Luyang,Zhao, Dadi The Korean Institute of Power Electronics 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.6

A constant voltage AC-DC converter based on digital assistant technology is proposed in this paper, which has rapid dynamic response capability. The converter operates in the PFM (Pulse Frequency Modulation) mode. According to the load state, the compensation current produced by the digital compensation module was injected into the CS pin to adjust the switching pulse width dynamically and improve the dynamic response. The control chip is implemented based on NEC $1{\mu}m$ 5V/40V HVCMOS process. A 5V/1.2A prototype has been built to verify the proposed control method. When the load jumps from idle to heavy, the undershoot time is only 7.4ms.