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Investigation of Different Conduction States on the Performance of NMOS-Based Power Clamp ESD Device
Wei Weipeng,Wang Yang,Chen Xijun,Zheng Yifei,Li Jieyu,Cao Pei,Cao Wenmiao 대한전기학회 2021 Journal of Electrical Engineering & Technology Vol.16 No.3
This article investigates the eff ects of diff erent gate coupling voltage and gate voltage duration on electro-static discharge (ESD) performance of several NMOS-based power rail protection devices. Through simulation and transmission line pulse (TLP) test, it is found that there are two modes in the conduction process of the main clamping NMOS: channel conduction state and parasitic NPN conduction state. Diff erent gate voltage and duration bring the two conduction states diff erent proportions in the whole working process, which give the device very diff erent robustness. The results show that under the condition of small gate voltage and long duration and the condition of large gate voltage and short duration, the device can achieve optimal performance because the trigger voltage can be reduced, and the parasitic NPN can be turned on in time to release most of the current