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조현묵 公州大學校工科大學生産技術硏究所 1996 論文集 Vol.5 No.-
A new kind of digital phase-locked loop(DPLL) is proposed, which consist of a modified 9-gate phase detector, a frequency multiplier and a loop filter. All of them are implemented in digital hardware without any analog component. The proposed DPLL has very fast lock-in speed and belongs to type II system and the shortcoming of the DPLL is that it enlarges phase noise by a factor of about 1.26. Because there is no analog element used and the circuit is not too complicated, the PLL can be integrated into one chip. With some improvement the loop candkfj have very wide acquisition range such as on the order of 10⁴or more.
조현묵,한일국,기장근 公州大學校工科大學生産技術硏究所 1996 論文集 Vol.5 No.-
In this thesis, Multi-way branch structure is designed to execute multiway branch instruction in the wireless LAN protocol processor. Because this structure substitute CAM(Content Addressable Memory) for target selection unit with label index information of program which branch in multiway according to system variables consist of flags & vectors. The CAM store a set of arbitrary variable conditions. Thus, this structure have feature which assign system value for multiway branch, can programming and reconfigure a set of variable conditions. The Desing of Multiway branch structure used cmn8a library which is 0.8um process of Compass tool, have about 9,500 gates and suitable for basis clock 80MHz of wireless LAN protocol processor.
Pipeline Subranging 아날로그 - 디지탈 변환기에 관한 연구
김종대,차균현,조현묵,백경갑,백인천 고려대학교 공학기술연구소 1992 고려대학교 생산기술연구소 생기연논문집 Vol.28 No.1
In this thesis, the design of high speed pipeline subranging A/D converter is presented. The A/D converter has the subranging structure in which the 8 bits are partitioned into higher 4 bits and lower 4 bits. The pipeline method is utilized to maintain the conversion speed as fast as that of flash structure. The error correction circuit is added to detect and correct the errors within ±8 LSB error range that may be generated in the 1st comparator. The converter has been designed using a double metal 1.5 ㎛ BiCMOS technology of Samsung Electronics Co. The performance of designed converter was evaluated by using AWB(Analog Work Branch) and SPICE simulator. Results shows a conversion speed of higher than 20 ㎒ and dissipates 390 ㎽ with 5 V single power supply. Its differential nonlinearity error (DNL) is below 1 LSB and integrator nonlinearity error (INL) is below 3.2 LSB for ±2 LSB error detection range and below 2.4 LSB for ±4 LSB error detection range.