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임인칠(In Chil Lim),이재민(Jae Min Lee) 한국정보과학회 1981 정보과학회논문지 Vol.8 No.4
In this paper, the realization method of multiple-valued combinational logic circuits whose faults are easily diagnosed and the algorithm of test set derivation for the diagnosis of solid stuck-at type multiplevalued faults is described. Furthermore this paper makes it easy to realize the multiple -valued logic circuits by representing the isolator circuit containing inputs that can set the converting standard value of unary operator. 本 論文은 故障診斷이 容易한 多値 組合論理回路의 實施에 關하여 論하고 Solid, stuck-at type 多値 故障診斷을 爲한 test set生成에 관한 algorithm을 提案하였다. 또한 unary operator 變換 基準値 設定이 可能한 入力을 가진 isolator 回路를 提案하여 實際 回路구성을 容易하게 하였다.
Characteristic Graph를 利用한 組合論理回路의 故障診斷 (pp.42-49)
임인칠(Lim In Chil),이양희(Lee Yang Hi),김한우(Kim Han Yoo) 한국정보과학회 1978 정보과학회논문지 Vol.5 No.1
This paper describes test-pattern generation and it's sequence for fan out-free Combinational logic network with multiple faults. The method for detecting multiple faults, in systematic way, is established by using characteristic graphs. This method is applied even in the case of fan out-reconvergent combinational logic networks. In this case, the network is decomposed into a set of fan out-free subnetworks characteristic graphs, and minimal test patterns are generated seperately. The each test set is combined and the test pattern for fan out-reconvergent networks are derived. According to corresponding characteristic graph, additional test patterns to detect multiple faults are simply derived.
임인칠(In Chil Lim),이성우(Sung Woo Lee) 한국정보과학회 1984 정보과학회논문지 Vol.11 No.1
多値論理函數에 대한 特殊函數로써 多値 threshold 函數를 정의하고, 이 함수의 構造的 性質을 解析하였다. 또 이 函數의 對稱性과 單調性을 설명하고 證明하였으며, 몇가지 관련된 예제들을 보였다. In this paper, the multiple-valued threshold function is defined as a kind of special multiple-valued logical function, and structural properties of this function are analized. Properties of symmetry and monotonicity of this threshold function are explained, and verified. Some of related examples are shown.
임인칠(Lim In Chil),김영수(Kim Young Soo) 한국정보과학회 1976 정보과학회논문지 Vol.3 No.1
This paper describes a logical design of ternary arithmetic circuits based on T-gates. A new circuit of T-gate is proposed which is improved in the stability of operation, and a ternary adder, subtracter, multiplier and divider using the T-gates are realized. The realization of the circuits is based on the Mod-3, system and the Signed Ternary system using digit 0, 1, 2 and -1. 0, +1 as arithmetic states.
임인칠(In Chil. Lim),김용훈(Yung Heun. Kim) 한국정보과학회 1980 정보과학회논문지 Vol.7 No.2
This paper proposes the algorithm to minimize the states of a incompletely specified sequential machine. In order to reduce the number of symbolic compatible from state minimization table, exclusion and its extended concept is used, then deletion is applied. And this paper shows that a prime closed set used to find the minimal from symbolic compatible, is identical with the concept of compatibility graph and that the minimal is obtained by compatibility graph. Also this paper shows that, if the number of symbolic compatible is increased such that graph is complex, the complexity is solved simply by use of the upper bound of the number of states.
N-値 多變數 論理回路의 實現을 爲한 Switching 函數
임인칠(Lim In Chil),정정화(Jung Jung Hwa) 한국정보과학회 1976 정보과학회논문지 Vol.3 No.2
This paper develops a new theory of multi-valued switching functions and presents simplification method of the multi-valued combinational circuits for realizing N-valued arithmetic units. Multi-valued adders based on the theory proposed here is presented. Switching funtions to composite 10-valued arithmetic units with BCD input are described which is taken into account of using together with 2-valued logic systems.
임인칠(In Chil Lim),이수영(Soo Young Lee) 한국정보과학회 1981 정보과학회논문지 Vol.8 No.1
本 論文에서는 多値 Logic Gate 즉 U-gate 를 使用한 Facsimile 信號의 帶域壓縮方式에 관하여 論한다. 즉 5値符號化方式인 多値 Digital 符號化方式을 제안하여 對稱 5値符號로 傳送하는 帶域壓縮方式을 시도하였다. Facsimile 信號를 送 · 受信하기 爲하여 必要한 Binary to 5-valued Encoder와 5-valued to Binary Decoder를 構成하였다. 그리고 Data Format는 Memory Capacity를 最小化시킬 수 있도록 하였다. 그 결과로서 다른 System에 비하여 좁은 bandwidth를 얻었고, 帶域壓縮率은 3値의 경우보다 約 5倍가 增加했다. 또 Hemory size는 A4 size paper의 경우에서 約 43KB에 해당한다. This paper deals with the band compression method of Facsimile signal based on Multivalued logic gate - U - gate. The principle of band compression, that is used in the proposed Fax system, is explained by the Multivalued digital coding method which is 5-valued coding method in this case. Binary to 5-valued Encoder and 5-valued to Binary Decoder are prepared for transmitting and receiving Fax signal. And data format is proposed to minimize the memory capacity. The results are that bandwith is narrower than that of other system, that band compression is increased about 5 times as large as that of ternary, and that memory size is about 43KB in case of A4 size paper. And the Fax system can be not only used as the communication terminal but also as the information storage devices.
Hazard - Free를 考慮한 多値順序論理回路 (pp.94-98)
임인칠(Lim In Chil),이수영(Lee Soo Young) 한국정보과학회 1978 정보과학회논문지 Vol.5 No.2
Multi-Valued(MV) sequential logic circuits are proposed which are free from HAZARD. In this paper, HAZARD is classified Function and Logic HAZARD, and MV switching function in which they are eliminated is described. Also, the basic MV memory elements which can be realized without HAZARD are presented, so that suggest the realizability in the large-scale MV logic system based on these elements.
임인칠(Lim In Chil),이양희(Lee Yang Hi),김한우(Kim Han yoo) 한국정보과학회 1977 정보과학회논문지 Vol.4 No.2
In this paper, an algorithm for generating the test set to detect all multiple stuck-at-faults in multiple-output combinational logic network is presented. The algorithm represented here is the procedure to generate the test patterns by following steps; First, the circuits constituted with the overlapped paths in the multiple output circuit are conception ally considered as lines and it is the pseudo-input lines of the multiple output circuit. Next, the test patterns of the overlapped-path circuits and those of the output circuits contained the overlapped-path circuits are generated. The Algorithm is derived from the conception of pseudo inputs by using the cause-effect equation. And it is shown that the test patterns can be generated by simpler procedure than other methods and the procedure of generating minimum test patterns is derived.