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고결,우창범,김민수,서영수,김신근,강명곤,신형철 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.5
In this paper, intrinsic characteristics of gate-all-around (GAA) nanoplate (NP) vertical FET (VFET) were investigated for single and multi-channel structure through 3-D technology computer-aided design (TCAD) simulations. The vertical device has strong immunity for the unprecedented short channel effects (SCE) and intrinsic gate delay compared with the lateral device owing to the flexible expansion channel in vertical direction. The proposed single and multi-channel NP VFETs (NP height = 40 nm) exhibit excellent characteristics with Ion/Ioff > 105, subthreshold swing (SS) < 73 mV/decade, and drain-induced barrier lowering (DIBL) < 60 mV/V.