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Cu Pillar 플립칩 접속부의 열 싸이클링 및 고온유지 신뢰성
김민영,임수겸,오태성,Kim, M.Y.,Lim, S.K.,Oh, T.S. 한국마이크로전자및패키징학회 2010 마이크로전자 및 패키징학회지 Vol.17 No.3
Cu pillar 범프와 Sn 패드로 구성된 플립칩 접속부를 형성한 후, Sn 패드의 높이에 따른 Cu pillar 플립칩 접속부의 열 싸이클링 및 고온유지 신뢰성을 분석하였다. Cu pillar 플립칩 접속부를 구성하는 Sn 패드의 높이가 5 ${\mu}m$에서 30 ${\mu}m$로 증가함에 따라 접속저항이 31.7 $m{\Omega}$에서 13.8 $m{\Omega}$로 감소하였다. $-45^{\circ}C{\sim}125^{\circ}C$ 범위의 열 싸이클을 1000회 인가한 후에도 Cu pillar 플립칩 접속부의 접속저항의 증가가 12% 이하로 유지되었으며, 열 싸이클링 시험전과 거의 유사한 파괴 전단력을 나타내었다. $125^{\circ}C$에서 1000 시간 유지시에도 Cu pillar 플립칩 접속부의 접속저항의 증가가 20% 이하로 유지되었다. For the flip chip joints processed using Cu pillar bumps and Sn pads, thermal cycling and high temperature storage reliabilities were examined as a function of the Sn pad height. With increasing the height of the Sn pad, which composed of the flip chip joint, from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance of the flip chip joint decreased from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$. Even after thermal cycles of 1000 times ranging from $-45^{\circ}C$ to $125^{\circ}C$, the Cu pillar flip chip joints exhibited the contact resistance increment below 12% and the shear failure forces similar to those before the thermal cycling test. The contact resistance increment of the Cu pillar flip chip joints was maintained below 20% after 1000 hours storage at $125^{\circ}C$.
Cu 범프와 Sn 범프의 접속구조를 이용한 RF 패키지용 플립칩 공정
최정열,김민영,임수겸,오태성,Choi, J.Y.,Kim, M.Y.,Lim, S.K.,Oh, T.S. 한국마이크로전자및패키징학회 2009 마이크로전자 및 패키징학회지 Vol.16 No.3
Cu pillar 범프를 사용한 플립칩 접속부는 솔더범프 접속부에 비해 칩과 기판사이의 거리를 감소시키지 않으면서 미세피치 접속이 가능하기 때문에, 특히 기생 캐패시턴스를 억제하기 위해 칩과 기판사이의 큰 거리가 요구되는 RF 패키지에서 유용한 칩 접속공정이다. 본 논문에서는 칩에는 Cu pillar 범프, 기판에는 Sn 범프를 전기도금하고 이들을 플립칩 본딩하여 Cu pillar 범프 접속부를 형성 한 후, Sn 전기도금 범프의 높이에 따른 Cu pillar 범프 접속부의 접속저항과 칩 전단하중을 측정하였다. 전기도금한 Sn 범프의 높이를 5 ${\mu}m$에서 30 ${\mu}m$로 증가시킴에 따라 Cu pillar 범프 접속부의 접속저항이 31.7 $m{\Omega}$에서 13.8 $m{\Omega}$로 향상되었으며, 칩 전단하중이 3.8N에서 6.8N으로 증가하였다. 반면에 접속부의 종횡비는 1.3에서 0.9로 저하하였으며, 접속부의 종횡비, 접속저항 및 칩 전단하중의 변화거동으로부터 Sn 전기도금 범프의 최적 높이는 20 ${\mu}m$로 판단되었다. Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.
칩 실장공정에 따른 Package on Package(PoP)용 하부 패키지의 Warpage 특성
정동명,김민영,오태성,Jung, D.M.,Kim, M.Y.,Oh, T.S. 한국마이크로전자및패키징학회 2013 마이크로전자 및 패키징학회지 Vol.20 No.3
Package on Package(PoP)용 하부 패키지에 대해 플립칩 본딩으로 칩을 기판에 실장한 패키지와 die attach film(DAF)을 사용하여 칩을 기판에 접착한 패키지의 warpage 특성을 비교하였다. 플립칩 본딩으로 칩을 기판에 실장한 패키지와 DAF를 사용하여 칩을 기판에 실장한 패키지는 솔더 리플로우 온도인 $260^{\circ}C$에서 각기 $57{\mu}m$와 $-102{\mu}m$의 warpage를 나타내었다. 상온에서 $260^{\circ}C$ 사이의 온도 범위에서 플립칩 실장한 패키지는 $-27{\sim}60{\mu}m$ 범위의 warpage를 나타내는 반면에, DAF 실장한 패키지는 $-50{\sim}-153{\mu}m$ 범위의 warpage를 나타내었다. The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpages of $57{\mu}m$ and $-102{\mu}m$, respectively. At the temperature range between room temperature and $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from $-27{\mu}m$ to $60{\mu}m$ and from $-50{\mu}m$ to $-15{\mu}m$, respectively.
고출력 LED 패키지의 Thermal Via 형성을 위한 Si 기판의 이방성 습식식각 공정
유병규,김민영,오태성,Yu, B.K.,Kim, M.Y.,Oh, T.S. 한국마이크로전자및패키징학회 2012 마이크로전자 및 패키징학회지 Vol.19 No.4
In order to fabricate through-Si-vias for thermal vias by using wet etching process, anisotropic etching behavior of Si substrate was investigated as functions of concentration and temperature of TMAH solution in this study. The etching rate of 5 wt%, 10 wt%, and 25 wt% TMAH solutions, of which temperature was maintained at $80^{\circ}C$, was $0.76{\mu}m/min$, $0.75{\mu}m/min$, and $0.30{\mu}m/min$, respectively. With changing the temperature of 10 wt% TMAH solution to $20^{\circ}C$ and $50^{\circ}C$, the etching rate was reduced to $0.067{\mu}m/min$ and $0.233{\mu}m/min$, respectively. Through-Si-vias of $500{\mu}m$-depth could be fabricated by etching a Si substrate for 5 hours in 10 wt% TMAH solution at $80^{\circ}C$ after forming same via-pattern on each side of the Si substrate. 습식공정으로 thermal via용 SI 관통 via를 형성하기 위해 TMAH 용액의 농도와 온도에 따른 Si 기판의 이방성 습식식각 거동을 분석하였다. TMAH 용액의 온도를 $80^{\circ}C$로 유지한 경우, 5 wt%, 10 wt% 및 25 wt% 농도의 TMAH 용액은 각기 $0.76{\mu}m/min$, $0.75{\mu}m/min$ 및 $0.30{\mu}m/min$의 Si 식각속도를 나타내었다. 10 wt% TMAH 용액의 온도를 $20^{\circ}C$와 $50^{\circ}C$로 유지시에는 각기 $0.07{\mu}m/min$와 $0.23{\mu}m/min$으로 식각속도가 저하하였다. Si 기판의 양면에 동일한 형태의 식각 패턴을 형성하여 $80^{\circ}C$의 10 wt% TMAH 용액에 장입하고 5시간 식각하여 깊이 $500{\mu}m$의 관통 via hole을 형성하였다.
김민영(M.Y. Kim),이용구(Y.G Lee),김윤년(Y.N. Kim),남창욱(C.W Nam),허윤석(Y.S.Heo) 대한기계학회 2015 대한기계학회 춘추학술대회 Vol.2015 No.11
Aortic dissection is a medical emergency situation requiring quick and proper treatments, otherwise patient can suddenly lead to death as a result of rupture of the aorta. The rupture can be triggered by many factors such as blood pressure, velocity, viscosity etc. and it is critical for patients to manage the internal and external factors acting on the blood vessels before the rupture begins. To control the factor like blood pressure, we need to set a threshold value for the safe zone for each patient to provide proper treatment guidelines. This important threshold can be obtained from the analysis of blood flow in the 3D model of aortic dissection. In this study, we analyzed CT images obtained from three patients who had three different type of the aortic dissection, respectively. The fluid flow simulations were done by using COMSOL Multiphysics. The results from the computational simulation are able to explain the blood flow characteristics and are well accordance with the expectation from the patient’s condition and types of aortic dissection.
Microfluidic Chip 유동특성을 이용한 PDMS 화학적 식각 및 상처 모델 구현
김민영(M.Y. Kim),정순우(S.W. Jung),이태재(T.J. Lee),허윤석(Y.S. Heo) 대한기계학회 2016 대한기계학회 춘추학술대회 Vol.2016 No.12
Lab on a chip using microfluidic has many advantages in comparison with existing in vitro experiment. It can make more in vivo like experiment by mimicking human internal environment. Because microfluidic has many advantages, many researcher mimic wound healing mechanisms inside microfluidic chips. But mostly research has conduct an experiment on flat channels without considered wounds depth. Wounds depth has a great influence upon the cell migration, when wounds healing. So in this research, I develop in vivo like wound healing chip having depth by chemical etching using laminar flow.