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Foreground Digital Calibration for Split-Capacitor DAC in SAR ADC
길명규(Myeonggyu Kil),김병호(Byoungho Kim) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
Split-capacitive digital-to-analog converter (CDAC) in successive-approximation-resistor (SAR) analogto- digital converter (ADC) suffers from the linearity degraded by the capacitor mismatch and by parasitic capacitances from the least-significant-bit (LSB) array. This paper proposes a foreground digital calibration scheme to compensate nonidealities of a split-CDAC. The linearity errors of a split-CDAC are estimated by switching logic based on the proposed digital calibration. Our proposed SAR ADC architecture uses 10.5-bit uncalibrated output to generate 10-bit calibrated output by adding error codes and by multiplying calibration factor. The behavioral simulation results of a 10.5-bit SAR ADC showed the DNL and the INL improved 0.31LSB and 1.27LSB, respectively. SNDR and SFDR were enhanced by 6.2dB and 13dB for each.
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A 10-Bit Split-SAR ADC with Perturbation-based Background Digital Calibration
길명규(Myeonggyu Kil),김병호(Byoungho Kim) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
It is hard to resolve the nonlinearity issue caused by the mismatch of bridge capacitor for split successiveapproximation-resistor (SAR) analog-to-digital converters (ADCs). Furthermore, the nonlinearity introduced by capacitor mismatch in the SAR ADCs affects more series problem on the ADC performance. This paper proposes a design method of a split SARADC with a background calibration to overcome both nonlinearities caused by the mismatches of a bridge capacitor as well as a binary-weighted capacitors. In this work, the same input signal is converted twice with additional capacitor, based on the perturbation manner. Then, the errors are calculated and those are alleviated in digital processing. The behavioral simulation results with the proposed 10bit split SAR ADC showed the enhanced DNL and INL as 0.69LSB and 0.75LSB, respectively. The SNDR and SFDR are improved by 4.72dB and 6.3dB, respectively.
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