Embedded PCI Local Bus Core의 VHDL을 이용한 설계 = Design of Embedded PCI Local Bus Core Based on VHDL

다국어 초록 (Multilingual Abstract)

A new challenge to hardware designer that requires not only already commercialized chip implementation but also customizable core development, merging, and implementation technology. Especially, in many areas of electronics engineering the growth of IC technology is remarkable. One of our concerns to develop the large amount of data transferring transaction IC technology is about BUS area. This paper will introduce a design of embedded PCI Local Bus Core described by VHDL. The methodology of using VHDL in developing system has an powerful merits because of its reusability.
This document will propose the structure of PCI Local bus and the methodology of the new our own core block structure of Embedded PCI Local bus core. Sometimes we need what we want to design in many hardware designations but unfortunately the commercialized chip-set have a big barrier to this our thought. So, This methodology to develop hardware can give us a choice to design what really we want to.
The main block of our embedded PCI core have some divided blocks like STATE MACHINE BLOCK, PARITY BLOCK, ADDRESS/COMMAND DECODE BLOCK, and READ/WRITE TRANSACTION BLOCK. The STATE MACHINE BLOCK is composed of changing its state: IDLE, B_BUSY, S_DPATA, TURN_AR, BACKOFF. All of these states make it possible for designer to easily see the current state of PCl bus. The PARITY BLOCK have two main functions : Parity generation function, Error generation function after parity checking. Then, The ADDRESS/COMMAND DECODE BLOCK will do decode PCI Address and Command. Lastly, READ/WRITE TRANSACTION BLOCK transfers the PCI data.
This mechanism of Embedded PCI Core can be varied according to the needs. Sometimes, The Core can be merged another sort of bus transaction just using the basis of transaction mechanism of PCI Bus. Another merit of PCI Bus as you knew already is the independence to CPU. So, The embedded Core block can be implemented to any Processor. For example, if we want to develop the Data Acquisition System just using micro-processor, We can develop a high speed and large amount transaction system using embedded PCI core to be contained Semi-customizable FPGA.
For escaping cost problems in developing core design we just use free core design methodology announced by Open-Core Organization. The evaluation version of Modesim tool can be used in this paper and it presents free compiler and free simulator for VHDL. But as mentioned some Free-Core Consortium so called Open-Core Organization, The needs for VHDL Synthesizer for free is necessary for designer to design without money.
In this paper, our simulation has been operated in a condition of RTL Levels. One of the big branch of simulation issues is about PCI Bus Transaction Modes. The modes are both Single Mode Transaction and Burst Mode Transaction. The Single Mode Transaction means every data transfer is taken place in every address transfer. But, The Burst Mode Transaction which is the basis of PCI bus mechanism means a continuous data block can be transferred after a single address transaction. Our Core simulations are having a results on both single mode and double mode. And another branch of simulation issues is about the distinguishment of three kinds of memories: 10 memory area, memory area, configuration memory area. All sorts of these simulations are performed and we acquired a good results.
After Simulation, The last step to make our own core is the process of synthesis. In this process, It has a main role what library of core we will arrange. In this paper, Our core can be synthesized with the library of ANAM 0.25 library for full custom and ALTER synopsys library for semi custom. Nowadays, for a low cost implementation of core design methodology it is more advantageous terms to use FPGA than ASIC. So, Our core optimization has been done using FPGA.

목차 (Table of Contents)

• 목차 = i
• 그림목록 = iii
• 표목록 = vi
• 용어 및 약어 = viii
• ABSTRACT = ix
• 1. 서론 = 1
• 2. PCI LOCAL BUS 구조 = 2
• 2.1 PCI(Peripheral Component Interface) 개요 = 2
• 2.2 PCI Local Bus의 특징 = 3
• 2.3 PCI Local Bus의 Signal Definition = 5
• 2.4 PCI BUS TRANSACTION = 11
• 2.5 PCI Configuration Transaction = 22
• 3. Embedded PCI Local Bus Core의 설계 = 39
• 3.1 PCI Target Sequencer Machine 설계 = 39
• 3.2 PCI Parity Process 설계 = 46
• 3.3 PCI Command Decoder design = 53
• 3.4 PCI Write/Read Procedure 설계 = 65
• 4. 결론 = 83
• 참고 문헌 = 84
• 부록 = 85