A sequential triggering technique in cascaded current source for low power 12-b D/A converter

다국어 초록 (Multilingual Abstract)

<B>Purpose</B> - The purpose of this paper is to introduce a low power digital-to-analog converter (DAC) by using a sequential triggering technique in cascaded current source. <B>Design/methodology/approach</B> - The block of current cell consists of current switch and source. A sequential switching on process is implemented with the current triggering technique in source. An experiment of 12-b 150-MS/s DAC has been integrated in a single-poly four-metal 0.35?µm CMOS process. <B>Findings</B> - Compared with conventional cell array in 12-b 150-MS/s DAC, the proposed cell array shows that more than 30 percent of power consumption is reduced in full digital bit operation with allowable linearity error of 0.4 LSB. <B>Originality/value</B> - This paper presents a new operation method of cell array in a current-steering digital-to-analog converter (DAC) to reduce the power consumption significantly.