BLE Application을 위한 55nm CMOS 공정의 고속, 저전력, Programmable Frequency Divider 설계 = A Design of low power, programmable, high speed Frequency Divider for BLE Application using 55nm CMOS

다국어 초록 (Multilingual Abstract)

In this paper, high speed CMOS Frequency Divider in Phase Locked Loop(PLL) of Bluetooth Low Energy(BLE) is proposed. This newly proposed True Single Phase Clock (TSPC) to reduce power and glitch. By changing schematic and size of PMOS, proposed TSPC could reduce glitch of output signal and adjust the shape of output signal. Using this new TSPC, Frequency Divider could get clearly divided output signal and low current. Also, this proposed programmable Frequency Divider using new TSPC. 4/5 synchronous dual-modulus divider is used to make Frequency Divider programmable. Proposed Frequency Divider can divide the signal 128 ~ 135 times. This programmable Frequency Divider can choose dividing ratio and can be helpful to make exact output signal of Frequency Divider in BLE application. Frequency Divider is designed for low power which use 202 μW at 1 V of input voltage.

목차 (Table of Contents)

• Abstract
• I. 서론
• II. 본론
• Ⅲ. 구현
• Ⅳ. 결론 및 향후 연구 방향
• 참고문헌