This paper describes a delay locked loop using flying butterfly delay cells that achieve a wide range operation, low jitter performance, low phase offset and accurate duty ratio. The proposed DLL uses a new structure consisting of a voltage controlled...
This paper describes a delay locked loop using flying butterfly delay cells that achieve a wide range operation, low jitter performance, low phase offset and accurate duty ratio. The proposed DLL uses a new structure consisting of a voltage controlled delay line(VCDL), phase detector(PD) and duty cycle corrector(DCC) for the reasonable operation. The DLL has been simulated in a 0.35um CMOS process.