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Invited: In-Line Electrical Characterization of Ultrathin Gate Dielectric Films
Cubaynes, F.;Passefort, S.;Eason, K.;Zhang, X.;Date, L.;Pique, D.;Conard, T.;Rothschild, A.;Schaekers, M. SEMI 2002 p.1-5
Alternative Smart-cut-like Process for Ultra-thin SOI Fabrication
Carr, W. N.;Chen, B.;Usenko, A. Y.;Chabal, Y. SEMI 2002 p.6-10
A Manufacturable Shallow Trench Isolation Process for Sub-0.2um DRAM Technologies
Lien, W. Y.;Yeh, W. G.;Li, C. H.;Tu, K. C.;Chang, I. H.;Chu, H. C.;Liaw, W. R.;Lee, H. F.;Chou, H. M.;Chen, C. Y. SEMI 2002 p.11-16
Controlling Lithographic Imaging Performance at Sub-100 nm CD with Optical Measurements
Grodnensky, I.;Enayati, S.;Manka, J.;Mizutani, S.;Slonaker, S. SEMI 2002 p.17-20
A Robust Shallow Trench Isolation (STI) with SiN Pull-Back Process for Advanced DRAM Technology
Li, C. H.;Tu, K. C.;Chu, H. C.;Chang, I. H.;Liaw, W. R.;Lee, H. F.;Lien, W. Y.;Tsai, M. H.;Liang, W. J.;Yeh, W. G. SEMI 2002 p.21-26
Flexible Polishing Surface (FPS) vs Rigid Polishing Surface (RPS) in CMP: Pros and Cons
Gotkis, Y.;Wei, D.;Kistler, R. SEMI 2002 p.27-32
Invited: A Simulation of Periodical Priority Dispatching of WIP for Product-mix Fabrication
Saito, K.;Arima, S. SEMI 2002 p.33-37
Characterization of Film Uniformity in LPCVD TEOS Vertical Furnace
Ekbundit, S.;Izzio, B. SEMI 2002 p.38-42
Immelman, R. E. SEMI 2002 p.43-48
Distributed WIP Control in Advanced Semiconductor Manufacturing
Qui, R.;Burda, R.;Chylak, R. SEMI 2002 p.49-54