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Block Structure Preserving Model Order Reduction
Yu, H.; He, L.; Tan, S. X.-D. IEEE, 2005 p.1-6
A General Method for Multi-Port Active Network Reduction and Realization
Liu, P.; Qi, Z.; Aviles, A.; Tan, S. X.-D. IEEE, 2005 p.7-12
Garg, A.; Gharpurey, R.; Charbon, E. IEEE, 2005 p.13-18
A Methodology for Modeling Lateral Parasitic Transistors in Smart Power ICs
Oehmen, J.; Hedrich, L.; Olbrich, M.; Barke, E. IEEE, 2005 p.19-24
Modeling and Simulation of Jitter in Phase-Locked Loops due to Substrate Noise
Kim, J. W.; Lu, Y.-C.; Dutton, R. W. IEEE, 2005 p.25-30
Behavioural Modeling and Simulation of a Switched-Current Phase Locked Loop
Wilson, P. R.; Wilcock, R.; Al-Hashimi, B.; Brown, A. D. IEEE, 2005 p.31-36
HDL based Simulation of Digital RF Frequency Synthesizers
Neyer, A.; Sappok, S.; Heinen, S. IEEE, 2005 p.37-42
Gu, B.; Gullapalli, K.; Hamm, S.; Mulvaney, B.; Lai, X.; Roychowdhury, J. IEEE, 2005 p.43-47
Accurate Behavioral Modeling Approach for PLL Designs with Supply Noise Effects
Kuo, C.-C.; Liu, C.-N. IEEE, 2005 p.48-53
Joeres, S.; Heinen, S. IEEE, 2005 p.54-59