In this paper, We designed a FD(Frequency Detector) for detecting the frequency of SPDIF signal and a PLL based on low-gain VCO (Voltage controlled Oscillator). The FD can detect the frequency using the preamble. If FD detects the preamble, stores the...
In this paper, We designed a FD(Frequency Detector) for detecting the frequency of SPDIF signal and a PLL based on low-gain VCO (Voltage controlled Oscillator). The FD can detect the frequency using the preamble. If FD detects the preamble, stores the count value in the memory block. The FD outputs 3bit signals corresponding to the detected frequency. The proposed PLL adjusts the bandwidth of the loop filter according to the frequency of the received SPDIF. Also, the gain of the VCO can be kept low by adjusting the capacitor. The PLL based on low gain VCO for SPDIF was designed using 55nm CMOS process.