TTL 시뮬레이터의 콤파일러 設計에 關한 硏究 = A study on the design of the compiler for a TTL simulator

국문 초록 (Abstract)

本 論文에서는 特殊 目的의 小型 電子計算機를 單一 뻐스線 方法에 의한 TTL 集積回路로 設計하였으며, 各 指令語의 길이를 16비트로 構成함으로써 더욱 簡便한 콤파일러를 硏究하였다.
또한 本 實驗에서 160nsec의 基本 週期를 擇함으로써, TTL IC의 動作時間에 따른 最適値와 記憶素子의 악세스 타임이 같게 되었고, 構成 回路도 간단하게 만들어졌으며, 모든 프로그램도 만조하게 처리되었다.

다국어 초록 (Multilingual Abstract)

The special mini-computer was designed with the one-bus line systems employing the integrated circuits, and was studied by the method of easily making the compiler in 16 bits with each instruction fields.
When the 160 nano seconds for a fundamental cycle were used, the optimum operating time for a TTL IC was egual to the access time for the main memory unit. As a result, the circuits were very simple, and the simulator functioned well for all the programs.