2K bit EPROM array and test patterns were fabricated by double poly silicon-gate NMOS technicue. The channel length and width of the EPROM cell were 6㎛ and 12㎛, respectively. The operation of peripheral circuits was simulated by SPICE and the expe...
2K bit EPROM array and test patterns were fabricated by double poly silicon-gate NMOS technicue. The channel length and width of the EPROM cell were 6㎛ and 12㎛, respectively. The operation of peripheral circuits was simulated by SPICE and the expected results were compared with experimental results. The optimal conditions of cell for programming were the drain voltage of 15-17V, gate voltage of 19-21V and the width of programming pulse of 30-35㎳, respectively. At that time, the threshold voltage was shifted from 1.6V(in erased state) to 9.4V (in programmed state).