Four Point Bending Test for Adhesion Testing of Packaging Strictures: A Review

Mahan, Kenny,Han, Bongtae The Korean Microelectronics and Packaging Society 2014 마이크로전자 및 패키징학회지 Vol.21 No.4

To establish the reliability of a packaging structures, adhesion testing of key interfaces is a critical task. Due to the material mismatch, the interface may be prone to delamination failure due to conditions during the manufacturing of the product or just from the day-to-day use. To assess the reliability of the interface adhesion strength testing can be performed during the design phase of the product. One test method of interest is the four-point bending (4PB) adhesion strength test method. This test method has been implemented in a variety of situations to evaluate the adhesion strength of interfaces in bimaterial structures to the interfaces within thin film multilayer stacks. This article presents a review of the 4PB adhesion strength testing method and key implementations of the technique in regards to semiconductor packaging.

Thermal Transient Characteristics of Die Attach in High Power LED Package

Kim Hyun-Ho,Choi Sang-Hyun,Shin Sang-Hyun,Lee Young-Gi,Choi Seok-Moon,Oh Yong-Soo The Korean Microelectronics and Packaging Society 2005 마이크로전자 및 패키징학회지 Vol.12 No.4

The rapid advances in high power light sources and arrays as encountered in incandescent lamps have induced dramatic increases in die heat flux and power consumption at all levels of high power LED packaging. The lifetime of such devices and device arrays is determined by their temperature and thermal transients controlled by the powering and cooling, because they are usually operated under rough environmental conditions. The reliability of packaged electronics strongly depends on the die attach quality, because any void or a small delamination may cause instant temperature increase in the die, leading sooner or later to failure in the operation. Die attach materials have a key role in the thermal management of high power LED packages by providing the low thermal resistance between the heat generating LED chips and the heat dissipating heat slug. In this paper, thermal transient characteristics of die attach in high power LED package have been studied based on the thermal transient analysis using the evaluation of the structure function of the heat flow path. With high power LED packages fabricated by die attach materials such as Ag paste, solder paste and Au/Sn eutectic bonding, we have demonstrated characteristics such as cross-section analysis, shear test and visual inspection after shear test of die attach and how to detect die attach failures and to measure thermal resistance values of die attach in high power LED package. From the structure function oi the thermal transient characteristics, we could know the result that die attach quality of Au/Sn eutectic bonding presented the thermal resistance of about 3.5K/W. It was much better than those of Ag paste and solder paste presented the thermal resistance of about 11.5${\~}$14.2K/W and 4.4${\~}$4.6K/W, respectively.

Experimental investigation of Scalability of DDR DRAM packages

Crisp, R. The Korean Microelectronics and Packaging Society 2010 마이크로전자 및 패키징학회지 Vol.17 No.4

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

DIMM-in-a-PACKAGE Memory Device Technology for Mobile Applications

Crisp, R. The Korean Microelectronics and Packaging Society 2012 마이크로전자 및 패키징학회지 Vol.19 No.4

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

Development of an Ultra-Slim System in Package (SiP)

Gao, Shan,Hong, Ju-Pyo,Kim, Jin-Su,Yoo, Do-Jae,Jeong, Tae-Sung,Choi, Seog-Moon,Yi, Sung The Korean Microelectronics and Packaging Society 2008 마이크로전자 및 패키징학회지 Vol.15 No.1

This paper reviews the current development of an ultra-slim SiP for Radio Frequency (RF) application, in which three flip chips, additional passive components and Surface Acoustic Wave (SAW) filters are integrated side-by-side. A systematic investigation is carried out for the design optimization, process and reliability improvement of the package, which comprises several aspects: a design study based on the 3D thermo-mechanical finite element analysis of the packaging, the determination of stress, warpage distribution, critical failure zones, and the figuration of the effects of material properties, process conditions on the reliability of package. The optimized material sets for manufacturing process were determined which can reduce the number of testing samples from 75 to 2. In addition the molded underfilling (MUF) process is proposed which not only saves one manufacturing process, but also improves the thermo-mechanical performance of the package compared with conventional epoxy underfilling process. In the end, JEDEC's moisture sensitivity test, thermal cycle test and pressure cooker tests have also been carried out for reliability evaluation. The test results show that the optimized ultra-slim SiP has a good reliability performance.

NIR Fluorescence Imaging Systems with Optical Packaging Technology

양우태,조상욱,정명영,최학수,Yang, Andrew Wootae,Cho, Sang Uk,Jeong, Myung Yung,Choi, Hak Soo The Korean Microelectronics and Packaging Society 2014 마이크로전자 및 패키징학회지 Vol.21 No.4

Bioimaging has advanced the field of nanomedicine, drug delivery, and tissue engineering by directly visualizing the dynamic mechanism of diagnostic agents or therapeutic drugs in the body. In particular, wide-field, planar, near-infrared (NIR) fluorescence imaging has the potential to revolutionize human surgery by providing real-time image guidance to surgeons for target tissues to be resected and vital tissues to be preserved. In this review, we introduce the principles of NIR fluorescence imaging and analyze currently available NIR fluorescence imaging systems with special focus on optical source and packaging. We also introduce the evolution of the FLARE intraoperative imaging technology as an example for image-guided surgery.

Magnetic and Thermal Evaluation of a Magnetic Tunneling Junction Current Sensor Package

Rhod, Eduardo,Peter, Celso,Hasenkamp, Willyan,Grion, Agner The Korean Microelectronics and Packaging Society 2016 마이크로전자 및 패키징학회지 Vol.23 No.4

Nowadays there are magnetic sensors in a wide variety of equipment such as computers, cars, airplanes, medical and industrial instruments. In many of these applications the magnetic sensors offer safe and non-invasive means of detection and are more reliable than other technologies. The electric current in a conductor generates a magnetic field detected by this type of sensor. This work aims to define a package dedicated to an electrical current sensor using a MTJ (Magnetic Tunnel Junction) as a sensing device. Four different proposals of packaging, three variations of the chip on board (CoB) package type and one variation of the thin small outline package (TSOP) were analyzed by COMSOL modeling software by simulating a brad range of current injection. The results obtained from the thermal and magnetic analysis has proven to be very important for package improvements, specially for heat dissipation performance.

Multi-Chip Packaging for Mobile Telephony

Bauer, Charles E. The Korean Microelectronics and Packaging Society 2001 마이크로전자 및 패키징학회지 Vol.8 No.2

This paper presents product level considerations for multichip packaging as a cost effective alternative to single chip packaging in the design and manufacture of mobile telephony products. Important aspects include component functionality and complexity, acquisition and logistics costs, product modularity and integration. Multichip packaging offers unique solutions and significant system level cost savings in many applications including RF modules, digital matrix functions and product options such as security, data storage, voice recognition, etc.

Comparisons of Interfacial Reaction Characteristics on Flip Chip Package with Cu Column BOL Enhanced Process (fcCuBE^®) and Bond on Capture Pad (BOC) under Electrical Current Stressing

Kim, Jae Myeong,Ahn, Billy,Ouyang, Eric,Park, Susan,Lee, Yong Taek,Kim, Gwang The Korean Microelectronics and Packaging Society 2013 마이크로전자 및 패키징학회지 Vol.20 No.4

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

Fully Embedded 2.4GHz Compact Band Pass Filter into Multi-Layered Organic Packaging Substrate

Lee, Seung-J.,Lee, Duk-H.,Park, Jae-Y. The Korean Microelectronics and Packaging Society 2008 마이크로전자 및 패키징학회지 Vol.15 No.1

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.