0.2 ${\mu}m$ Wide-Head T-Gate PHEMT 제작에 관한 연구

전병철,윤용순,박현창,박형무,이진구,Jeon, Byeong-Cheol,Yun, Yong-Sun,Park, Hyeon-Chang,Park, Hyeong-Mu,Lee, Jin-Gu 대한전자공학회 2002 電子工學會論文誌-SD (Semiconductor and devices) Vol.39 No.1

본 논문에서는 서로 다른 dose를 갖는 이중 노광 방법을 사용한 전자빔 묘화 방법을 이용하여 0.2 ㎛의 wide-head T-게이트를 갖는 PHEMT를 제작하였다. 0.2 ㎛의 게이트 길이와 1.3 ㎛의 게이트 머리의 크기를 갖는 wide-head T-게이트를 형성하기 위하여 PMMA/P(MMA-MAA)/PMMA의 3층 레지스트 구조를 사용하였다. 0.2 ㎛의 게이트 길이와 80 ㎛의 단위 게이트 폭 및 4개의 게이트 핑거를 갖는 PHEMT의 DC 특성으로 323 ㎃/㎜의 드레인 전류 밀도 및 232 mS/㎜의 최대 전달 컨덕턴스를 얻었다. 또한 동일한 소자의 RF 특성으로 40 ㎓에서 2.91 ㏈의 S/sub 21/ 이득과 11.42 ㏈의 MAG를 얻었으며, 전 이득 차단 주파수와 최대 공진 주파수는 각각 63 ㎓와 150 ㎓였다. n this paper, we have fabricated pseudomorphic high electron mobility transistors (PHEMT) with a 0.2 ${\mu}{\textrm}{m}$ wide-head T-shaped gate using electron beam lithography by a dose split method. To make the T-shape gate with gate length of 0.2 ${\mu}{\textrm}{m}$ and gate head size of 1.3 ${\mu}{\textrm}{m}$ we have used triple layer resist structure of PMMA/P(MMA-MAA)/PMMA. The DC characteristics of PHEMT, which has 0.2 ${\mu}{\textrm}{m}$ of gate length, 80 ${\mu}{\textrm}{m}$ of unit gate width and 4 gate fingers, are drain current density of 323 ㎃/mm and maximum transconductance 232 mS/mm at $V_{gs}$ = -1.2V and $V_{ds}$ = 3V. The RF characteristics of the same device are 2.91㏈ of S21 gain and 11.42㏈ of MAG at 40GHz. The current gain cut-off frequency is 63GHz and maximum oscillation frequency is 150GHz, respectively.ively.

MCU용 Fast 256Kb EEPROM 설계

김용호,박헌,박무훈,하판봉,김영희,Kim, Yong-Ho,Park, Heon,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2015 한국정보통신학회논문지 Vol.19 No.3

본 논문에서는 MCU(Micro Controller Unit) IC를 위한 50ns 256Kb EEPROM 회로를 설계하였다. 설계된 EEPROM IP는 기준전압을 이용한 차동증폭기 형태의 DB(Data Bus) 센싱 회로를 제안하여 읽기 동작시 데이터 센싱 속도를 빠르게 하였으며, DB를 8등분한 Distributed DB 구조를 적용하여 DB의 기생 커패시턴스 성분을 줄여 DB의 스위칭 속도를 높였다. 또한 기존의 RD 스위치 회로에서 5V 스위치 NMOS 트랜지스터를 제거함으로써 읽기 동작 시 BL의 프리차징 시간을 줄여 액세스 시간을 줄였고 데이터 센싱 시 DB 전압과 기준전압 간의 전압차 ${\Delta}V$를 0.2VDD 정도 확보하여 출력 데이터의 신뢰도를 높였다. 매그나칩반도체 $0.18{\mu}m$ EEPROM 공정으로 설계된 256Kb EEPROM IP의 액세스 시간은 45.8ns 이며 레이아웃 면적은 $1571.625{\mu}m{\times}798.540{\mu}m$이다. In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

Fabrication of a Bottom Electrode for a Nano-scale Beam Resonator Using Backside Exposure with a Self-aligned Metal Mask

Lee, Yong-Seok,Jang, Yun-Ho,Bang, Yong-Seung,Kim, Jung-Mu,Kim, Jong-Man,Kim, Yong-Kweon The Korean Institute of Electrical Engineers 2009 Journal of Electrical Engineering & Technology Vol.4 No.4

In this paper, we describe a self-aligned fabrication method for a nano-patterned bottom electrode using flood exposure from the backside. Misalignments between layers could cause the final devices to fail after the fabrication of the nano-scale bottom electrodes. A self-alignment was exploited to embed the bottom electrode inside the glass substrate. Aluminum patterns act as a dry etching mask to fabricate glass trenches as well as a self-aligned photomask during the flood exposure from the backside. The patterned photoresist (PR) has a negative sidewall slope using the flood exposure. The sidewall slopes of the glass trench and the patterned PR were $54.00^{\circ}$ and $63.47^{\circ}$, respectively. The negative sidewall enables an embedment of a gold layer inside $0.7{\mu}m$ wide glass trenches. Gold residues on the trench edges were removed by the additional flood exposure with wet etching. The sidewall slopes of the patterned PR are related to the slopes of the glass trenches. Nano-scale bottom electrodes inside the glass trenches will be used in beam resonators operating at high resonant frequencies.

이용악 시에 나타난 길의 의미

노용무 현대문학이론학회 2004 現代文學理論硏究 Vol.0 No.21

Ever since making his debut with 「패배자의 소원(A Hope Of A Loser)」(1935) in the Journal『Shinin-munhak』, Lee Yong-ak worte a lot of poem and remains really active in his creative work. His works on the whole poeticized the kernel situation of his times through the impoverished conditions of rural communities under coercive Japanese imperial rule and the consequent people's nomadism This paper aims to consider the "Road" motif as the coherent relation and the literary convention in Lee Yong-ak's poetic system. Cnsidering this problem, this paper seek the meaning of Road by literary immanent methods, and search of symbolism and paths in the Road. The Road is a search for self-identity by problematic character as poetic speaker, and for self-consciousness in a world degraded. This symbolism develops two paths in Lee Yong-ak's poetry, one path to the South, another to the north. It is homology between Lee Yong-ak's life and the path of Road in his poetry. Also the meaning of are changed in his historical environment.

Characterization of Inkjet-Printed Silver Patterns for Application to Printed Circuit Board (PCB)

Shin, Kwon-Yong,Lee, Minsu,Kang, Heuiseok,Kang, Kyungtae,Hwang, Jun Young,Kim, Jung-Mu,Lee, Sang-Ho The Korean Institute of Electrical Engineers 2013 Journal of Electrical Engineering & Technology Vol.8 No.3

In this paper, we describe the analysis of inkjet-printed silver (Ag) patterns on epoxy-coated substrates according to several reliability evaluation test method guidelines for conventional printed circuit boards (PCB). To prepare patterns for the reliability analysis, various regular test patterns were created by Ag inkjet printing on flame retardant 4 (FR4) and polyimide (PI) substrates coated with epoxy for each test method. We coated the substrates with an epoxy primer layer to control the surface energy during printing of the patterns. The contact angle of the ink to the coated epoxy primer was $69^{\circ}$, and its surface energy was 18.6 $mJ/m^2$. Also, the substrate temperature was set at $70^{\circ}C$. We were able to obtain continuous line patterns by inkjet printing with a droplet spacing of $60{\mu}m$. The reliability evaluation tests included the dielectric withstanding voltage, adhesive strength, thermal shock, pressure cooker, bending, uniformity of line-width and spacing, and high-frequency transmission loss tests.

A comparative study on the inhibitory effects of mast cell-mediated allergic reactions by artificially cultured and wild Acanthopanax senticosus

Yi, Jin-Mu,Jeong, Hyun-Ja,Shim, Kyung-Shik,Lee, Kang-Yong,Kim, Jeong-Sook,Zheng, Cui,Tomoko, Jippo,Lee, Young-Mi Kyung Hee Oriental Medicine Research Center 2000 International journal of oriental medicine Vol.1 No.2

We compared the effect between CAS and WAS(root, stem) on mast cell-mediated allergic reaction. CAS, WAS-root and WAS-stem, significantly inhibited compound 48/80-induced systemic allergic reaction(1g/kg) and histamine release from RPMC(1mg/ml). CAS, WAS-root and WAS-stem also inhibited passive cutaneous anaphylactic reaction. In addition, IgE-induced $TNF-{\alpha}$ secretion from RBL-2H3 was inhibited by pretreatment of CAS, WAS-root or WAS-stem$(0.01{\mu}g/ml)$. Taken together, inhibitory effect on mast cell-mediated allergic reactions of WAS-root is greater than those of WAS-stem but less than those of CAS.

Risk Assessment of 5-Chloro-2-Methylisothiazol-3(2H)-One/2-Methylisothiazol-3(2H)-One (CMIT/MIT) Used as a Preservative in Cosmetics

Kim, Min Kook,Kim, Kyu-Bong,Lee, Joo Young,Kwack, Seung Jun,Kwon, Yong Chan,Kang, Ji Soo,Kim, Hyung Sik,Lee, Byung-Mu Korean Society of ToxicologyKorea Environmental Mu 2019 Toxicological Research Vol.35 No.2

The mixture of 5-chloro-2-methylisothiazol-3(2H)-one (CMIT) and 2-methylisothiazol-3(2H)-one (MIT), CMIT/MIT, is a preservative in cosmetics. CMIT/MIT is a highly effective preservative; however, it is also a commonly known skin sensitizer. Therefore, in the present study, a risk assessment for safety management of CMIT/MIT was conducted on products containing 0.0015% of CMIT/MIT, which is the maximum MIT level allowed in current products. The no observed adverse effect level (NOAEL) for CMIT/MIT was 2.8 mg/kg bw/day obtained from a two-generation reproductive toxicity test, and the skin sensitization toxicity standard value for CMIT/MIT, or the no expected sensitization induction level (NESIL), was $1.25{\mu}g/cm^2/day$ in humans. According to a calculation of body exposure to cosmetics use, the systemic exposure dosage (SED) was calculated as 0.00423 mg/kg bw/day when leave-on and rinse-off products were considered. Additionally, the consumer exposure level (CEL) amounted to $0.77512{\mu}g/cm^2/day$ for all representative cosmetics and $0.00584{\mu}g/cm^2/day$ for rinse-off products only. As a result, the non-cancer margin of safety (MOS) was calculated as 633, and CMIT/MIT was determined to be safe when all representative cosmetics were evaluated. In addition, the skin sensitization acceptable exposure level (AEL)/CEL was calculated as 0.00538 for all representative cosmetics and 2.14225 for rinse-off products; thus, CMIT/MIT was considered a skin sensitizer when all representative cosmetics were evaluated. Current regulations indicate that CMIT/MIT can only be used at concentrations 0.0015% or less and is prohibited from use in other cosmetics products. According to the results of this risk assessment, the CMIT/MIT regulatory values currently used in cosmetics are evaluated as appropriate.

동기식 256-bit OTP 메모리 설계

이용진,김태훈,심외용,박무훈,하판봉,김영희,Li, Long-Zhen,Kim, Tae-Hoon,Shim, Oe-Yong,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2008 한국정보통신학회논문지 Vol.12 No.7

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$. 본 논문에서는 자동차 전장용 Power IC, 디스플레이 구동 칩, CMOS 이미지 센서 등의 응용분야에서 필요로 하는 동기식 256-bit OTP(one-time programmable) 메모리를 설계하였다. 동기식 256-bit OTP 메모리의 셀은 고전압 차단 트랜지스터 없이 안티퓨즈인 NMOS 커패시터와 액세스 트랜지스터로 구성되어 있다. 기존의 3종류의 전원 전압을 사용하는 대신 로직 전원 전압인 VDD(=1.5V)와 외부 프로그램 전압인 VPPE(=5.5V)를 사용하므로 부가적인 차단 트랜지스터의 게이트 바이어스 전압 회로를 제거하였다. 그리고 프로그램시 전류 제한 없이 전압 구동을 하는 경우 안티퓨즈의 ON 저항 값과 공정 변동에 따라 프로그램 할 셀의 부하 전류가 증가한다. 그러므로 프로그램 전압은 VPP 전원 선에서의 저항성 전압 감소로 인해 상대적으로 증가하는 문제가 있다. 그래서 본 논문에서는 전압 구동 대신 전류 구동방식을 사용하여 OTP 셀을 프로그램 할 때 일정한 부하전류가 흐르게 한다. 그래서 웨이퍼 측정 결과 VPPE 전압은 5.9V에서 5.5V로 0.4V 정도 낮출 수 있도록 하였다. 또한 기존의 전류 감지 증폭기 대신 Clocked 인버터를 사용한 감지 증폭기를 사용하여 회로를 단순화시켰다. 동기식 256-bit OTP IP는 매그나칩 반도체 $0.13{\mu}m$ 공정을 이용하여 설계하였으며, 레이아웃 면적은 $298.4{\times}3.14{\mu}m2$이다.

저전압 SoC용 밴드갭 기준 전압 발생기 회로 설계

이태영,이재형,김종희,심외용,김태훈,박무훈,하판봉,김영희,Lee, Tae-Young,Lee, Jae-Hyung,Kim, Jong-Hee,Shim, Oe-Yong,Kim, Tae-Hoon,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2008 한국정보통신학회논문지 Vol.12 No.1

The band-gap reference voltage generator which can be operated by low voltage is proposed in this paper. The proposed BGR circuit can be realized in logic process by using parasitic NPN BJTs because a $Low-V_T$ transistors are not necessary. The proposed BGR circuit is designed and fabricated using $0.18{\mu}m$ triple-well process. The mean voltage of measured VREF is 0.72V and the three sigma$(3{\sigma})$ is 45.69mv. 본 논문에서는 $Low-V_T$ 트랜지스터가 필요 없는 로직공정으로 Parasitic NPN BJT를 이용하여 저 전압에서 동작 가능한 밴드갭 기준전압 발생기 회로를 제안하였다. $0.18{\mu}m$ triple-well 공정을 사용한 BGR회로를 측정 한 결과 VREF의 평균전압은 0.72V $3{\sigma}$는 45.69mV로 양호하게 측정되었다.

화상처리를 이용한 디버링 가공물의 품질 측정

송무건,백재용,신관수,유송민 한국공작기계학회 2001 한국공작기계학회 춘계학술대회논문집 Vol.2001 No.-

In this study a vision system with image processing method have been introduced to find the edge radius of curvature. It was applied to inspect the edge quality of the de burring process product with brush grinding. Size of data was found to be critical in calculating the radius of curvature. Results using laser measurement system were compared.