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A Technique for Reducing Power Consumption in IC by Test Vector Ordering
Shuanghua Huang,Xiaomin Li 보안공학연구지원센터 2016 International Journal of Smart Home Vol.10 No.4
This paper considers the issue of high power dissipation in test mode, and puts forward a novel technique based on the reordering of test vectors. This approach considers both the circuit structure and test set. The proposed approach uses a weight to quantify the relationship between the switching of each input and the internal switching activity, then reorder test set based on these weights. Results of experiments show reductions of the switching activity ranging from 17.06% to 69.22% during external test application.
Research on SOC Test Bus Allocation Algorithm under the Constraint of Temperature
Xiaomin Li,Shuanghua Huang 보안공학연구지원센터 2015 International Journal of Hybrid Information Techno Vol.8 No.8
The main concern is over rising temperature during the testing of complex system-on-chip (SOC), this paper studies SOC wrapper and test access mechanism (TAM), and proposes an improved algorithm of TAM assignment under the constraints of temperature. The algorithm uses temperature superposition method and adds compression process. This algorithm can find the test structure that uses shorter test time.