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鄭均樂 弘益大學校 科學技術硏究所 1994 科學技術硏究論文集 Vol.5 No.-
In this paper, we study the technology mapping of a lookup-table-based field programmable gate arrays and analyze conventional techniques. For an effective technology mapping, logic optimization is preprocessed like the conventional gate arrays. The main goal is to minimize either the total number of LUTs for an area optimization or the number of levels of LUTs for a delay optimization. Our mapping algorithm consists of three parts. First, the decomposition algorithm transforms an original network into a two-input network. Second, the labeling algorithm determines each node's level for a delay optimization. Finally, the LUT mapping algorithm generates the logically equivalent network of K-LUTs.
고집적회로 설계에서 최적의 플로어플랜을 위한 효율적인 Branch-and-Bound 방법
鄭均樂 弘益大學校 科學技術硏究所 1993 科學技術硏究論文集 Vol.3 No.-
The floorplan of a VLSI chip is comprised of several building blocks. Each of these may have several possible realizations with each realization having different dimensions. To realize a VLSI chip, one has to select a realization for each of its building blocks. This selection together with the floorplan determine the overall dimensions of the chip. For nonslicing floorplans, branch-and-bound can be used to get an optimal(minimum area) solution. Both the block order and dimension order affect the number of nodes in the state space tree that are actually expanded during a branch-and-bound search. In this paper, we suggest the best combination of block ordering and dimension ordering for efficient branch-and-bound algorithm.
VCG에서 사이클 최소화를 위한 모듈의 방향에 관한 연구
鄭均樂 弘益大學校 科學技術硏究所 1991 科學技術硏究論文集 Vol.1 No.-
The routability of a given placement of modules can be improved by flipping some or all of modules. A routing channel typically consists of a rectangular space between two parallel rows of terminals. Each module has a set of nets and can be flipped about its vertical axis. A vertical constraint graph(VCG) is associated with an assignment of nets to terminals. Many channel routing algorithms require the VCG acyclic. When modules can be flipped, two interesting problem arise : by flipping modules 1) can we get and acyclic VCG? 2) can we get a VCG with minimunm number of vertices in cycles?. In this paper, we show that these problems are NP-hard and develope heuristics.
鄭均樂,全基煥 弘益大學校 科學技術硏究所 1992 科學技術硏究論文集 Vol.2 No.-
Global Register Allocation plays a major role in determining the efficacy of an Optimizing Compiler. Instructions involving only register operands are shorter and faster than those involving memory operands. Therefore, efficient utilization of the limited number of hardware register is important in generating good code. The register allocator attempts to map the registers in such a way as to minimize the number of memory references. In this paper, we compare several register allocation methods and have designed and implemented the global register allocator using priority-based graph coloring.
鄭均樂 弘益大學校 科學技術硏究所 1994 科學技術硏究論文集 Vol.4 No.-
Suppose we construct a computer dictionary. The words in the dictionay need to be stored in some data structure for frequent searches. Since the amount of storage required is very huge and words are searched very often, that structure must occupy less storage and provide fast searches. In the paper, we propose an efficient data structure for storing strings. This structure can be used for storing dictionary words and circuit paths.
鄭均樂,金東出 弘益大學校 科學技術硏究所 1995 科學技術硏究論文集 Vol.6 No.-
After modules are placed according to some placement algorithm, circuit performance and routability can be affected by either flipping modules about their vertical and/or horizontal axes of symmetry or rotating modules while keeping the module placement fixed. In performance sensitive applications, it is desirable to minimize the maximum wire length. Chong and Sahni showed that this problem is NP-hard. In this paper we have developed an Genetic-Algorithm for the problem of minimizing maximum wire length by flipping mudules.
鄭均樂,全基煥 弘益大學校 科學技術硏究所 1997 科學技術硏究論文集 Vol.8 No.-
Trees are very poular data structures with applications in sorting, searching, compiling, hierarchical database models, organizational charts, and so on. Visual displays of trees that make structural relationships explicit are more useful than listings of trees. To draw trees on monitor screens of limited size, we need to consider area and aesthetical aspect simultaneously. In this research, we have implemented algorithms for drawing binary and general trees. We also have developed an algorithm for general trees with vertically expandable nodes of arbitrary sizes. We increase the height of nodes minimally so that nodes and edges do not overlap.
HFC 케이블 TV 망에서 노드선택을 위한 Greedy 휴리스틱 연구
鄭均樂 弘益大學校 科學技術硏究所 2007 科學技術硏究論文集 Vol.18 No.-
The CATV network has traditionally delivered downward broadcasting signals from distribution centers to subscribers. Recently, the increased utilization of upward channels has expanded broadband services such as Internet and telephone services. This upward channel is vulnerable to ingress noises. When the noises from the children nodes accumulated in an amplifier exceeds a certain level, the signal can no longer be separated from the noise. In this case, the node has to be cut off to prevent the noise from propagating further. When each node has some profit value, the node selection problem(NSP) is to select nodes so that the noise in each node does not exceed the given threshold value and the sum of those profits can be maximized. The NSP has shown to be NP-hard. Thus if the number of nodes on the network is large, it is impossible to find the optimal solution as the execution time for finding the optimal solution grows exponentially. In this paper, we have proposed greedy heuristics to find the near-optimal solution for NSP and has shown experimental results.
전력 소모를 감소시키기 위한 게이트 크기 재결정에 관한 알고리즘 연구
鄭均樂,李炯日 弘益大學校 科學技術硏究所 1999 科學技術硏究論文集 Vol.10 No.1
The gate resizing is the problem of finding load drive capabilities of all gates such that a given delay limit is satisfied and the total cost in terms of area and/or power consumption is minimal. After this step, power consumption can be further reduced by gate resizing - larger gates are replaced by smaller ones that have higher delay but lower power consumption and the circuits timing constraints are still obeyed. In this paper, we have proposed new algorithm for gate resizing problem which is superior to Chen's algorithm.
POPS 네트워크 구조에서의 Bitonic 정렬 알고리즘에 관한 연구
鄭均樂,宋命根 弘益大學校 科學技術硏究所 2001 科學技術硏究論文集 Vol.12 No.-
The partitioned optical passive stars network (POPS) is an optical interconnection network for a multiprocessor computer. It uses multiple OPS couplers which can receive an optical signal from any one of its source nodes and transmit the received signal to all of its destination nodes. A message can be sent from one processor to the other in a single slot. A POPS(d, g) network partitions the n processors into g groups of size d and the choice of g and d affects the interconnection cost and the bandwidth. Sorting is one of the most important operations performed by a computer and many parallel sorting algorithms have been investigated for various parallel computer architectures. In this paper, we have studied how to implement efficiently the bitonic sort on a POPS network.