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Kaneko, Mineo,Miyauchi, Hiroyuki,Park, Choon Sik 대한전자공학회 1996 APCCAS:Asia Pacific Conference on Circuits And Sys Vol.1 No.1
A systematic procedure to configure fault tolerant systolic arrays based on Triple Modular Redundancy in mixed spatial-temporal domain is proposed. While the triplication of the original dependence graph brings complicated data communication, unforced and forced link sharing schemes are introduced and detailed design procedure utilizing them for reducing link complexity is proposed.