CMOS 연산 증폭기 및 비교기 회로의 자동 설계

신현우,김천호,김득경,신창호,신경욱 國立金烏工科大學校附設生産技術硏究所 1994 産業技術開發硏究 Vol.10 No.-

The paper describes a CMOS analog circuit design tool, K_ACD(Kumoh_Analog Circuits Designer), and design results. The K_ACD was developed for automatic design of fundamental analog circuit blocks such as comparator, unbuffered OP AMP, and buffered OP AMP. For given specifications and process parameters, it computes bias currents, transistor sizes, voltage gain, and power dissipation, then SPICE simulations are automatically carried out. Some design examples show usefulness of the K_ACD in analog circuit designs.

나리屬의 花粉學的 觀察

辛昌男,方在旭,吳炅煥 충남대학교 자연과학연구소 1979 學術硏究誌 Vol.6 No.2

Pollen morphology of Lilium 1ancifolium L. leichtlinii var, tigrinum and L, distichum was examined by the light microscopy in conjunction differences of pollen Character in Kwangnung, The pollen character of three species was similar except the grain size, The average polar axis and equatrial axis of L,lancifolium showed the highest values among three species and L.distichum was lowest. The differences of them in three species were significant judging from the F-test (p<0.05). And the differences in size of pollen grain in three species were significant (P<0.05). It was possible for grain size to classify the pollen of species of Lilium.

웨이브렛 변환영역에서 FCM-VQ를 이용한 영상부호화에 관한 연구

신경철,이동욱 慶南專門大學 1997 論文集 Vol.25 No.1

증후성 단일 소심부뇌경색의 임상적 및 방사선학적 양상

신원철,이태규,노용우,오재욱,장대일,정경천 대한노인병학회 2000 Annals of geriatric medicine and research Vol.4 No.3

N점 FFT를 O(N)의 시간복잡도로 계산하는 새로운 병렬처리 구조

신경욱 金烏工科大學校 1991 論文集 Vol.12 No.-

본 논문에서는 고해상도 고속 퓨리어 변환 (fast Fourier transform)의 실시간 계산을 위한 새로운 VLSI 어레이 구조를 제안하고, 제안된 어레이 구조를 이용하여 ?? point FFT를 계산하기위한 완전한 알고리즘을 제안한다. 이를 위하여, 2차원 어레이의 index 공간(i,j)를 새로운 index 공간 (??)와 (??)로 매핑하기 위한 새로운 index 매핑 방법을 고안하였다. 제안된 어레이 구조는 다음과 같은 특징을 갖는다. 첫째, N-point FFT 계산에 소요되는 시간 복잡도 (Time Complexity)가 ??이다. 이는 기존의 2차원 어레이의 ??보다 ??배 개선된 것이며 따라서, N이 큰 고해상도 FFT의 경우에 연산시간이 크게 개선된다. 둘째, 제안된 어레이 구조는 2차원 sub-array 모듈들이 병렬 및 파이프라인 방식으로 동작하므로 데이터처리의 병렬성이 극대화된다. 넷째, 처리요소의 기본 연산을 기존의 버터플라이 연산 대신에 새로운 반쪽 버터플라이 연산으로 정의함으로써 데이터 셔플링 시간이 반으로 줄었으며, 처리요소의 연산참여율이 50%에서 100%로 두배 향상되었다.

2차원 어레이를 이용한 Vector-radix 2차원 고속 DCT의 효율적인 VLSI 구현

신경욱,전흥우,강용섬 金烏工科大學校 1993 論文集 Vol.14 No.-

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform(VR-FCT), and its VLSI implementation. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. It has the time complexity of ?? for (N X N) 2-D DCT, where ?? is the number of non-zero digits in canonic-signed digit (CSD) code. An array core based on the proposed array algorithm is designed with ISRC 1.5㎛ double metal N-Well CMOS technology. A hierarchical design approach based on Bit-Slice Unit (BSU) is adopted to achieve simple design and regular interconnections. The designed array core consists of 64 PE's arranged in 8 rows 8 columns, and it contains about 98,000 transistors on an area of 138㎜²excluding control logic block. From simulation results, it is estimated that (8X8) 2-D DCT(??) can be computed in about 0.88㎲ec at 50MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.

디지털 무선 모뎀용 적응 결정귀환 등화기 설계

신경욱,안병규,김호하 金烏工科大學校 1998 論文集 Vol.19 No.-

This work describes an ASIC implementation of adaptive decision-feedback equalizer (ADFE) which is applicable to wide band digital wireless modems. A new approach based on redundant binary (RB) arithmetic is devised for an efficient implementation of complex-number filter which is a key functional block of ADFE. The proposed RB complex-number filter structure reduces the critical path delay of ADFE. as well as leads to a more compact realization than conventional methods. Also, the carry-propagation free (CPF) operations of the RB arithmetic enhance its speed. To demonstrate the proposed approach, a prototype chip set which is composed of feed-forward equalizer module (FFEM) and decision-feedback equalizer module (DFEM) has been designed. Each module contains two complex-number filter taps along with their coefficient update circuits, and can be cascaded to implement longer filter taps for high bit-rate applications. The chip set was modeled and verified using VHDL. and synthesized using 0.8-㎛ sea-of-gate (SOG) array library.

한국 소비자원 상담에 나타난 주택유형별 소비자 불만분석

김선욱;신경주 한양대학교 2007 韓國 生活 科學 硏究 Vol.27 No.1

The purpose of this study is to provide basic data for the improvement of residential quality and the protection of consumers by resolving consumer problems in single-family houses, apartments, row houses, multiplex houses, and studio apartments. The analytic data used for the research were 1073 formal complaints filed at the Korea Consumer Agency from January 1 to December 31, 2000. The results are as follows: 1) Consumers in single-family houses complained about housing management such as water leakage, consumers in apartments complained about housing economics which is related to the cancellation of contract, consumers in row houses complained about housing management such as water leakage, consumers in multiplex houses complained about housing economics which is related to the cancellation of contract and consumers in studio apartments complained about housing economics which is related to the cancellation of contract. 2) Complains about housing management highly appeared in all types of houses, especially in single-family houses and row houses, except in studio apartments; complains about housing economics appeared in all types of houses, though less frequent in apartments, multiplex houses, and studio apartments; and complaints about housing environment appeared less in all types of houses, though more frequent in single-family houses than other types of houses. 3) Gonsumer problems commonly founded were problems related to repairing defects, contracts, sale and purchase, and house environment.

4-비트 리코딩 기법을 이용한 64-b x 67-b 병렬 승산기 설계

김득경,신경욱 金烏工科大學校 1994 論文集 Vol.15 No.-

This paper describes a design of 67-b parallel mutiplier using 4-bit recoding scheme. The multiplier supports both signed integer and unsigned integer, and operates in 2-stage pipelined manner. By adopting the 4-bit recoding scheme, which is an extension of the modified Booth algorithm (MBA), it requires only 22 partial products to be added, as compared with 32 partial products in the MBA. In order to reduce hardware complexity and to obtain better interconnect regularity, we utilize an optimized 4 : 2 carry-save adder (CSA) tree structure with the sign vector concept devised in this paper. The designed multiplier is modeled and verified using Verilog hardware description language (HDL). The multiplier can be used as a high-performance multiplier core for the arithmetic unit of microprocessors and general-purpose digital signal processors.

MMS를 기반으로 한 ICCP 프로토콜 구현

장병욱,한경덕,장경수,신동렬 成均館大學校 科學技術硏究所 2000 論文集 Vol.51 No.1

Advances in computer and communications technology have been successfully applied by power utilities in the development of information systems. Many of these systems are dedicated to meeting the specific needs of particular utility functions. Furthermore these systems have evolved based on proprietary communication protocols and thus been operated on various vendor-specific platform. These characteristics make communications between systems difficult, complex, and costly. In order to promote and facilitate interoperability between computer systems supplied to the electric utility industry, EPRI(Electric Power Research Institute) initiated the new standard protocol called ICCP(Inter-Center Control Communications Protocol) which specified the use of MMS(Manufacturing Message Specification) for use of in utility field devices or communication between control centers. This paper addresses the characteristics, modeling and implementation of objects associated with ICCP and MMS.