RISS 학술연구정보서비스

검색
다국어 입력

http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.

변환된 중국어를 복사하여 사용하시면 됩니다.

예시)
  • 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
  • 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
닫기
    인기검색어 순위 펼치기

    RISS 인기검색어

      검색결과 좁혀 보기

      선택해제

      오늘 본 자료

      • 오늘 본 자료가 없습니다.
      더보기
      • 무료
      • 기관 내 무료
      • 유료
      • DC Voltage Sensorless Control Strategy of Grid-tied Two-stage Three-phase Photovoltaic System

        Jianhua Yuan,Feng Gao,Houlei Gao 전력전자학회 2011 ICPE(ISPE)논문집 Vol.2011 No.5

        The variable dc voltage generated by photovoltaic (PV) array can be harnessed as much as possible through the well-known two-stage inversion in gridtied configuration, where the controlled dc-link voltage can be maintained stably to ensure the desired low harmonic ac output. Traditionally, the front-end dc Boost converter generally operates to track the maximum power point (MPP) of PV array by directly measuring the input current and voltage, meanwhile the rear-end inverter is controlled to generate sinusoidal output current and keep dc-link voltage unchanged. The PV voltage and dc-link voltage are measured to assist the accurate control of whole PV generation system. This paper proposes a novel control strategy to eliminate both dc voltage sensors assumed in traditional two-stage grid-tied PV system while not downgrade the system performance with regard to the MPPT accuracy and ac output quality. Matlab simulations verified the proposed control strategy with captured waveforms to illustrate its performance.

      • Dead-Time Elimination and Zero Common Mode Voltage Operation of Neutral-Point-Clamped Inverter

        Feng Gao,Jianhua Yuan,Ding Li,Poh Chiang Loh,Houlei Gao 전력전자학회 2011 ICPE(ISPE)논문집 Vol.2011 No.5

        This paper presents the dead-time elimination scheme for modulating neutral-point-clamped inverter. Unlike the dead-time compensation methods reported for mitigating negative effects induced by dead-time insertion, the proposed scheme simply separates each pair of switches by treating every switch independently and triggers the corresponding switches per phase according to the judged current direction. The removal of dead-time interval, together with the introduction of an appropriate modulation scheme, can then help mitigate switching common mode voltage, even without those narrow alternating spikes generated by common dead-time insertion in traditional pulsewidth modulation (PWM) techniques.

      연관 검색어 추천

      이 검색어로 많이 본 자료

      활용도 높은 자료

      해외이동버튼