RISS 검색 - 국내학술지논문

1
TIME DOMAIN ANALYSIS OF CARBON NANOTUBE INTERCONNECTS BASED ON DISTRIBUTED RLC MODEL

DAVOOD FATHI,BEHJAT FOROUZANDEH 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2009 NANO Vol.4 No.1
This paper introduces an accurate analysis of time domain response of carbon nanotube (CNT) interconnects based on distributed RLC model that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous principle calculations, accurate expressions for the transfer function of these lines and their time domain response have been presented. It has been shown that the second-order transfer function cannot represent the distributed behavior of the long CNT interconnects, and the fourth-order approximation offers a better result. Also, the time response of a driven long CNT interconnect versus length and diameter have been studied. The obtained results show that the overshoot increases and the time delay decreases with increasing the CNT diameter, such that with the diameter value of 10 nm for a 3.3 mm CNT interconnect, the maximum overshoot value reaches about 95% of the amplitude of the driver input. On the contrary, the overshoot increases and the time delay decreases with decreasing the length of the CNT, such that with the length value of 1 mm for a 5 nm diameter CNT interconnect, the maximum overshoot reaches about 90% of the amplitude of the driver input.
2
A NEW REPEATER INSERTION TECHNIQUE FOR THE OPTIMIZATION OF GLOBAL INTERCONNECTS IN NANO-VLSI

DAVOOD FATHI,BEHJAT FOROUZANDEH 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2009 NANO Vol.4 No.6
In this paper, a new method for global interconnects optimization in nanoscale VLSI circuits using unequal repeater (buffer) partitioning technique is presented. The optimization is performed with the energy-delay product minimization at 65, 90, and 130 nm technology nodes and various loads, using the genetic algorithm (GA) of MATLAB. The results show more improvements of the total propagation delay with respect to the traditional equal buffer partitioning technique. This improvement is obvious for 90 and 130 nm, and with increasing capacitive load, the improvement will be achieved for 65 nm.
3
NEW ENHANCED NOISE ANALYSIS IN ACTIVE MIXERS IN NANOSCALE TECHNOLOGIES

DAVOOD FATHI,BEHJAT FOROUZANDEH,NASSER MASOUMI 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2009 NANO Vol.4 No.4
In this paper, a new enhanced noise analysis for active mixers in nanoscale technologies, based on the variations of the two parameters W/L (transistor size) and fLO (local oscillator frequency) is presented. In this study, two important sections of an active mixer, the switching pair and the transconductor are considered. It is shown that the noise generated by the switching pair and the transconductor is reduced with the technology scaling from 90 nm to 45 nm. Also, it is shown that the variations of the noise generated by the switching pair due to W/L variations in a wide range of local oscillator frequency and in different technology nodes is less than the variations of the noise generated by the transconductor, which shows the importance of the transconductor in the generation of the total mixer output noise. For extracting the noise relations, the contribution of the gate resistance noise to the gate and drain total current noises is considered, whereas this noise is usually assumed to be an independent source in the literature.
4
ACCURATE ANALYSIS OF GLOBAL INTERCONNECTS IN NANO-FPGAs

DAVOOD FATHI,BEHJAT FOROUZANDEH 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2009 NANO Vol.4 No.3
This paper introduces a new technique for analyzing the behavior of global interconnects in FPGAs, for nanoscale technologies. Using this new enhanced modeling method, new enhanced accurate expressions for calculating the propagation delay of global interconnects in nano-FPGAs have been derived. In order to verify the proposed model, we have performed the delay simulations in 45 nm, 65 nm, 90 nm, and 130 nm technology nodes, with our modeling method and the conventional Pi-model technique. Then, the results obtained from these two methods have been compared with HSPICE simulation results. The obtained results show a better match in the propagation delay computations for global interconnects between our proposed model and HSPICE simulations, with respect to the conventional techniques such as Pi-model. According to the obtained results, the difference between our model and HSPICE simulations in the mentioned technology nodes is (0.29–22.92)%, whereas this difference is (11.13–38.29)% for another model.

상세검색

RISS 보유자료

상세검색

해외전자자료

연관 검색어 추천