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A Vertical Double-Diffused MOSFET
김종오,최연익,손호태,성만영,Kim, Jong-Oh,Choi, Yearn-Ik,Sohn, Ho-Tae,Sung, Man-Young The Institute of Electronics and Information Engin 1986 전자공학회논문지 Vol.23 No.6
In this paper, we discuss fabrication and characteristics of the Vertical Double diffused MOS(VDMOS) transistor. The epi layers of starting wafers are 18~22\ulcorner in thickness and 8~12\ulcornercm in resistivity. The channel regions are defined through the self-aligned double diffusion process. The characteristics of the fabricated VDMOS are breakdown voltage of 240V, threshold voltage of 2V, on-resistance of 226\ulcornerand transconductance of 3x10**-3 mho.
A Study on the 80V BICMOS Device Fabrication Technology
박치선,차승익,최연익,정원영,박용,Park, Chi-Sun,Cha, Seung-Ik,Choi, Yearn-Ik,Jung, Won-Young,Park, Yong The Institute of Electronics and Information Engin 1991 전자공학회논문지-A Vol.28 No.10
In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.