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직접 확산 통신을 위한 기저 대역 MODEM의 VLSI 구현
김건,조중휘,Kim, Geon,Cho, Joong-Hwee 대한전자공학회 1997 電子工學會論文誌, C Vol.c34 No.8
In tis paper, w eproposed a modeling for direct-sequence spread communication base band modem in RT-level VHDL and implemented in a one-chip VLSI and tested. The transmitter modulates with DQPSK modulation method and spreads a modulated signal with 32-bit PN code into 1.152MHz. The receiver de-spreads a signal using 32-tap matched filter and recovers with DQPSK demodulation method. The digital frequency synthesizer generates the sine signal and the cosine signal of 2.304MHz with ROM tables in the size of 7$\^$*/256 and 6$\^$*/256, respectively. The implemented VLSI has been verified a BER with 10$\^$-4/ at E$\_$b//N$\_$o/ of 13dB with a SPW fixed design model and fabricated in the 0.8.mu.m KG6423 gate array with a VHDL model.
FSM 설계를 위한 하드웨어 흐름도와 하드웨어 기술 언어에 관한 연구
이병호,조중휘,정정화,Lee, Byung-Ho,Cho, Joong-Hwee,Chong, Jong-Wha 대한전자공학회 1989 전자공학회논문지 Vol. No.
본 논문에서는 논리 설계 자동화를 위한 레지스터 전송 레벨의 하드웨어 흐름도와 하드웨어 기술언어 SDL-II (symbolic description language)를 각각 제안한다. SDL-II는 일반화된 FSM(finite state machine)의 동작 및 구조적 특성을 제안하는 하드웨어 흐름도로 표현하고 이의 각 기호에 1대 1 대응하며 제어부와 데이타 전송부를 함께 기술하도록 구문을 설정한다. 또한 여러가지 설계 요구조건을 하드웨어 흐름도로 표현하고 이를 SDL-II로 기술하여 본 논문의 유효성을 보인다. This paper describes hardware flow-chart and SDL-II, which are register-transfer level, to automate logic design. Hardware flow-chart specifies behavioral and structural charaterstics of generalized FSMs (Finite State Machine) usin the modified ASM (Algorithmic State Machnine) design techniques. SDL-II describes the hardware flow-chat which specifies the control and the data path of ASIC(Application Specific IC). Also many examples are enumerated to illustrate the features of hardware flow-chart and SDL-II.
DVB용 2K/8K FFT의 Stratix EP1S25F672C6 FPGA 구현
민종균,조중휘,Min, Jong-Kyun,Cho, Joong-Hwee 대한전자공학회 2007 電子工學會論文誌-SD (Semiconductor and devices) Vol.44 No.8
본 논문에서는 유럽형 DTV용 FFT를 설계하고 Stratix EP1S25F672C6 FPGA를 이용하여 구현하였다. SIC 구조를 사용하여 FFT를 구현하였으며, 사용된 SIC 구조는 특정 알고리즘 처리 연산을 수행하기 위한 처리기와 RAM 메모리, 레지스터들과 전체 블록 및 부분 블록의 동작을 통제하기 위한 조정기로 구성된다. 디자인된 FFT는 DVB-T 표준사양을 만족하도록 2K/8K FFT 연산을 처리 가능하며, 선택적으로 1/4, 1/8, 1/16, 1/32의 4가지 보호구간 모드를 모두 지원한다. 구현된 FFT는 사용된 Stratix FPGA에 전체 로직의 12%, 전체 메모리의 53%를 사용한다. In this paper, we designed FFT for European DTV and implemented system with Stratix EP1S25F672C6 FPGA At the implemented FFT, we used SIC architecture. SIC architecture is composed of algorithm-specific processing element, RAM memory, registers, and a central or distributed control unit. Designed FFT was acceptable either 2K or 8K point FFT processing, and is selectable guard interval such as 1/4, 1/8, 1/16, 1/32. Consequently, it was suitable for the standard of DVB-T(Digital Terrestrial Video Transmission System) specification. It resulted in 12% of total logic gate and 53% of total memory bit in Stratix device.
정준희,구창모,조중휘,Jeong, Jun Hee,Gu, Chang Mo,Cho, Joong Hwee 한국반도체디스플레이기술학회 2021 반도체디스플레이기술학회지 Vol.20 No.2
The TCD is used as one of the indicators for determining whether TSV Hole is defective. If the TCD is not normal size, it can lead to contamination of the CMP equipment or failure to connect the upper and lower chips. We propose a deep learning model for measuring the TCD. To verify the performance of the proposed model, we compared the prediction results of the proposed model for 2461 via holes with the CD-SEM measurement data and the prediction results of the existing model. Although the number of trainable parameters in the proposed model was about one two-thousandth of the existing model, the results were comparable. The experiment showed that the correlation between CD-SEM and the prediction results of the proposed model measured 98%, the mean absolute difference was 0.051um, the standard deviation of the absolute difference was 0.045um, and the maximum absolute difference was 0.299um on average.
Light Field Rendering 기술을 이용한 간이 광학현미경
김다희 ( Da-hee Kim ),조중휘 ( Joong-hwee Cho ) 한국정보처리학회 2020 한국정보처리학회 학술대회논문집 Vol.27 No.2
Light Field Rendering 을 이용하여 성능이 떨어지는 Low resolution 카메라 장비로 얻는 영상의 한계를 극복하고, Image Processing 기술로 직접 조정해야 해결할 수 있는 수차 및 성능 문제 해결한다. 저가형 장비, 렌즈를 사용하여도 컴퓨터기반 처리를 이용하여 물리적인 한계를 극복한 간이 광학현미경을 만들고자 함. 3D print 를 이용한 뼈대구조를 만들고, 저렴한 raspberry pi 임베디드 플랫폼을 이용하여 설계도만 있다면, 누구나 쉽게 만들 수 있기에 많은 사람들이 이 분야에 더 쉽게 다가설 수 있게 한다.
임재영,김건,김영진,김호영,조중휘,Lim, Jae-Young,Kim, Geon,Kim, Young-Jin,Kim, Ho-Young,Cho, Joong-hwee 대한전자공학회 1996 전자공학회논문지-A Vol.33 No.7
This paper has been presented a design of a POCSAG decoder in RT-level VHDL and implemented in a FPGA chip, and tested. In a single clock of 76.8KHz, the decoder receives all the data of the rate of 512/1200/2400bps and has maximum 2-own frames for service enhancement. To improve decoder performance, the decoder uses a preamble detection cosidering 9% frequency tolerance, a SCW detction and a ICW detection at each 4 bit. The decoder also corrects a address data and a message data up to 2 bits and proposes the PF (preamble frequency) error for saving battery. The decoder increases a battery life owing to turn off RF circuits when the preamble signal is detected with nises. The chip has been designed in RT-level VHdL, synthesized into logic gates using power view$^{TM}$ of viewlogic software. The chip has been implemented in an ALTERA EPF81188GC232-3 FPGA chip with 98% usability, and fully tested in shield room and field room. The chip has been proved that the wrong detection numbers of preamble of noises are significantly reduced in the pager system using PDI 2400 through the real field test. The receiving performance is improved by 20% of aaverage, compared with other existing systems.
스테레오 영상 보행자 인식 시스템의 후보 영역 검출을 위한 GP-GPU 기반의 효율적 구현
정근용,정준희,이희철,전광길,조중휘,Jeong, Geun-Yong,Jeong, Jun-Hee,Lee, Hee-Chul,Jeon, Gwang-Gil,Cho, Joong-Hwee 대한임베디드공학회 2013 대한임베디드공학회논문지 Vol.8 No.2
There have been various research efforts for pedestrian recognition in embedded imaging systems. However, many suffer from their heavy computational complexities. SVM classification method has been widely used for pedestrian recognition. The reduction of candidate region is crucial for low-complexity scheme. In this paper, We propose a real time HOG based pedestrian detection system on GPU which images are captured by a pair of cameras. To speed up humans on road detection, the proposed method reduces a number of detection windows with disparity-search and near-search algorithm and uses the GPU and the NVIDIA CUDA framework. This method can be achieved speedups of 20% or more compared to the recent GPU implementations. The effectiveness of our algorithm is demonstrated in terms of the processing time and the detection performance.
안상근,서태규,전광길,조중휘,Ahn, Sang-Geun,Seo, Tae-Kyu,Jeon, Gwang-Gil,Cho, Joong-Hwee 대한임베디드공학회 2016 대한임베디드공학회논문지 Vol.11 No.6
In this paper, we propose an improved single view metrology (SVM) algorithm to accurately measure the height of objects. In order to accurately measure the size of objects, vanishing points have to be correctly estimated. There are two methods to estimate vanishing points. First, the user has to choose some horizontal and vertical lines in real world. Then, the user finds the cross points of the lines. Second, the user can obtain the vanishing points by using software algorithm such as [6-9]. In the former method, the user has to choose the lines manually to obtain accurate vanishing points. On the other hand, the latter method uses software algorithm to automatically obtain vanishing points. In this paper, we apply image resizing and edge sharpening as a pre-processing to the algorithm in order to improve performance. The estimated vanishing points algorithm create four vanishing point candidates: two points are horizontal candidates and the other two points are vertical candidates. However, a common image has two horizontal vanishing points and one vertical vanishing point. Thus, we eliminate a vertical vanishing point candidate by analyzing the histogram of angle distribution of vanishing point candidates. Experimental results show that the proposed algorithm outperforms conventional methods, [6] and [7]. In addition, the algorithm obtains similar performance with manual method with less than 5% of the measurement error.