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WCDMA용 67-dB DR, 1.2-V, $0.18-{\mu}m$ 시그마-델타 모듈레이터 설계
김현중,유창식,Kim, Hyun-Jong,Yoo, Chang-Sik 대한전자공학회 2007 電子工學會論文誌-SD (Semiconductor and devices) Vol.44 No.6
[ $0.18-{\mu}m$ ] CMOS 공정에서 1.2-V 2차 Full-Feedforward 구조의 ${\Sigma}{\Delta}$ 모듈레이터를 설계하였다. Full-Feedforward 구조는 Op-Amp의 성능 요구치를 크게 경감시키기 때문에 저전압 저전력 ${\Sigma}{\Delta}$ 모듈레이터를 만들기에 적합한 구조로 세계적으로 많이 채택되고 있는 추세이다. 그리고, Top-Down 설계 기법을 적용하여 ${\Sigma}{\Delta}$ 모듈레이터를 설계하였는데, 이를 위하여 Op-Amp의 유한한 DC-Gain과 Bandwidth 등 여러 가지 비이상적 효과들을 모델링하여 전달함수를 유도하였다. [ $0.18-{\mu}m$ ] CMOS 1.2-V 2nd-order ${\Sigma}{\Delta}$ modulator with full-feedforward topology is designed. Using full-feedforward topology makes op-amp performance requirements much less stringent, therefore it has been adopted as a good candidate for low-voltage low-power applications throughout the world. Also, ${\Sigma}{\Delta}$ modulator is designed with top-down design approach, therefore various nonideal effects of op-amp are modeled in this paper.
김창남(Chang Nam Kim),유창식(Chang Sik Yu),한명식(Myoung Sik Han),이한일(Han Il Lee),조영미(Young Mee Cho),김온자(On Ja Kim),유빈(Bin Yoo),김진천(Jin Cheon Kim) 대한소화기학회 1998 대한소화기학회지 Vol.30 No.3
Polyarteritis nodosa(PAN) is a systemic vasculitis affecting mainly small and medium sized arteries. Over 50% of the cases, PAN may cause gastrointestinal symptoms. Main gastrointestinal symptoms are abdominal pain, vomiting, nausea, diarrhea and melena. A very rare case of isolated PAN affecting the jejunum, manifested as stricture, is reported. A 55-year-old woman with prior history of hypertension presented herself complaining of abdominal pain and weight loss. Radiologic studies showed a segmental narrowing of the jejunum. At the time of surgery, 3cm length narrowed, thickened fibrotic intestinal wall was found at 110cm distal to the Treitz ligament. Pathological finding showed acute necrotizing vasculitis of a medium sized artery. (Korean J Gastroenterol 1997; 30:411-414)
Tracking analog-to-digital 변환기를 이용한 digital phase-locked loop
차수호,유창식,Cha, Soo-Ho,Yoo, Chang-Sik 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.9
A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter. 본 논문에서는 1.6Gb/s에서 동작하는 digitally controlled phase-locked loop (DCPLL)를 제안한다. DCPLL은 일반적인 아날로그 PLL과 tracking analog-to-digital 변환기를 결합한 구조이다. 제안한 DCPLL에서는 tracking ADC의 출력이 voltage controlled oscillator (VCO)의 제어 전압을 생성한다. 일반적으로 사용되는 digital PLL (DPLL)은 digitally controlled oscillator (DCO)와 time-to-digit converter (TDC)로 구성된다 DCO와 TDC를 사용한 DPLL은 시간 스텝이 작을 수 록 jitter 특성이 향상되지만 전력소모는 커진다. 이 논문에서 제안한 DCPLL은 DPLL의 핵심요소인 DCO와 TDC를 사용하지 않았기 때문에 jitter, 면적, 전력소모 측면에서 유리하다. DCPLL은 $0.18\mu$m 4-metal CMOS공정을 이용하여 제작하였고 면적은 1mm $\times$0.35mm를 차지한다. 1.8V 단일 전원전압으로 정상동작에서는 59mW, power-down 모드에서는 $984\mu$W 전력을 소모하고 16.8ps rms jitter를 갖는다.
서영석(Young-Suk Seo),유창식(Chang-Sik Yoo) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
Using 1/8-rate linear phase detector, 8-Gb/s Clock and data recover circuit is implemented in this paper. The proposed CDR(Clock and Data Recovery) phase detector uses 1/8-rate clock, and expands UP & DOWN pulse width than conventional linear-type CDR phase detector. Thereby the proposed phase detector speeds up CDR. Also the proposed CDR has the function of 1:8 de-multiplexing.
비교기 그룹의 기준전압을 치환하며 두 번의 비교를 진행하는 스토캐스틱 아날로그-디지털 변환기
유원준(Won-jun Yoo),전민기(Min-ki Jeon),김찬규(Chan-gyu Kim),유창식(Chang-sik Yoo) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.6
To design a flash analog-to-digital converter (ADC), offset cancellation technique for comparator is necessary, but stochastic flash ADC can be designed without any offset cancellation circuit. It is a big merit of stochastic ADC. Nevertheless, stochastic ADC is not practical because of the need of large number of comparator. The proposed method can reduce the number of comparator in half using the property of comparator offset distribution.
석지환(Ji-Hwan Seok),유창식(Chang-Sik Yoo) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
In this paper a 600㎷ low supply voltage filter is presented. The filter is designed with 2.11㎒ cut-off frequency. The 4<SUP>th</SUP> order filter consists of two 2<SUP>nd</SUP> order biquadratic cells. Input and output of biquadratic cell is VDD/2 to maximize signal swing and the input common mode voltage of opamp is VDD/4 to suit for low voltage. Capacitor array is used to tune cut-off frequency, and the filter is designed using 0.13㎛ CMOS technology.