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혼합형 조합 회로용 고장 시뮬레이션 시스템의 설계 및 구현
박영호(Park Young Ho),손진우(Sohn Jin Woo),박은세(Park Eun Sei) 한국정보처리학회 1997 정보처리학회논문지 Vol.4 No.1
This paper presents a fast fault simulation system for detecting stuck-at fault in mixed-level combinational logic circuits with gate level and switch-level primitives. For a practical fault simulator, the circuit types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well-known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.