소아암환자에서 발생하는 급성 복증

박병관,문석배,정성은,정규환,박귀원,Park, Byung-Kwan,Moon, Suk-Bae,Jung, Sung-Eun,Jung, Kyu-Whan,Park, Kwi-Won 대한소아외과학회 2009 소아외과 Vol.15 No.2

Catheter related and perianal problems are common surgical complications encountered during the treatment of pediatric malignancies. However acute surgical abdominal emergencies are rare. The aim of this study is to review acute surgical abdominal complications that occur during the treatment of childhood malignancies. Out of a total of 1,222 patients who were newly diagnosed with malignant disease, between January 2003 and May 2008, there were 10 patients who required surgery because of acute abdominal emergencies. Their medical records were reviewed retrospectively. Hematologic malignancies were present in 7 patients (4 leukemia, 2 lymphoma, 1 Langerhans cell histiocytosis) and solid tumors in 3 patients (1 adrenocortical carcinoma, 1 desmoplastic small round cell tumor, 1 rhabdomyosarcoma). Seven patients had intestinal obstruction, two had gastrointestinal perforation and one, typhlitis. Intestinal obstructions were treated with resection of the involved segment with (N=2) or without (N=3) enterostomy. Two patients had enterostomy alone when resection could not be performed. Intestinal perforation was treated with primary repair. Typhlitis of the ascending colon was treated with ileostomy. Right hemicolectomy was necessary the next day because of the rapidly progressing sepsis. Three patients are now alive on chemotherapy and one patient was lost to followed-up. Among six patients who died, five died of their original disease progression and one of uncontrolled sepsis after intestinal perforation. Although rare, acute surgical abdominal complications can occur in childhood malignancies. Rapid and accurate diagnosis and appropriate operation are required for effective treatment of the complications.

A Micro-Architecture Simulator

박병관,배상덕,서대화,윤용호,Park, Byung Kwan,Bae, Sang Duck,Seo, Dae Wha,Yoon, Yong Ho The Institute of Electronics and Information Engin 1987 전자공학회논문지 Vol.24 No.3

The microprogram is the key technology of the implementation of the processor's control unit. But the coding and testing it is the most tedious process in the developing a new computer system. We developed the conversational micro architecture simulator(C-MAS) in order to use it as a microprogram development tool and a run time analyzer of the microprogram. We discuss the hardware description language(HDL) for a smulation, the design constraints of the C-MAS, and the user interface of it in this paper. We used the C language as the description language, and developed it on the berkeley UNIX4.2.

233-비트 이진체 타원곡선을 지원하는 암호 프로세서의 저면적 구현

박병관,신경욱,Park, Byung-Gwan,Shin, Kyung-Wook 한국정보통신학회 2017 한국정보통신학회논문지 Vol.21 No.7

This paper describes a design of cryptographic processor supporting 233-bit elliptic curves over binary field defined by NIST. Scalar point multiplication that is core arithmetic in elliptic curve cryptography(ECC) was implemented by adopting modified Montgomery ladder algorithm, making it robust against simple power analysis attack. Point addition and point doubling operations on elliptic curve were implemented by finite field multiplication, squaring, and division operations over $GF(2^{233})$, which is based on affine coordinates. Finite field multiplier and divider were implemented by applying shift-and-add algorithm and extended Euclidean algorithm, respectively, resulting in reduced gate counts. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 49,271 gate equivalents (GEs), and the estimated maximum clock frequency is 345 MHz. One scalar point multiplication takes 490,699 clock cycles, and the computation time is 1.4 msec at the maximum clock frequency. NIST 표준에 정의된 이진체(binary field) 상의 233-비트 타원곡선을 지원하는 타원곡선 암호(elliptic curve cryptography; ECC) 프로세서를 설계하였다. 타원곡선 암호 시스템의 핵심 연산인 스칼라 점 곱셈을 수정형 Montgomery ladder 알고리듬을 이용하여 구현함으로써 단순 전력분석에 강인하도록 하였다. 점 덧셈과 점 두배 연산은 아핀(affine) 좌표계를 기반으로 유한체 $GF(2^{233})$ 상의 곱셈, 제곱, 나눗셈으로 구현하였으며, shift-and-add 방식의 곱셈기와 확장 유클리드 알고리듬을 이용한 나눗셈기를 적용함으로써 저면적으로 구현하였다. 설계된 ECC 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였다. $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 합성한 결과 49,271 GE로 구현되었고, 최대 345 MHz의 동작 주파수를 갖는다. 스칼라 점 곱셈에 490,699 클록 사이클이 소요되며, 최대 동작 주파수에서 1.4 msec의 시간이 소요된다.

SiGe JFET과 Si JFET의 전기적 특성 비교

박병관,양현덕,최철종,심규환,Park, B.G.,Yang, H.D.,Choi, C.J.,Shim, K.H. 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.11

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

SiGe/Si/SiGe Channel을 이용한 JFET의 전기적 특성

박병관,양현덕,최철종,김재연,심규환,Park, B.G.,Yang, H.D.,Choi, C.J.,Kim, J.Y.,Shim, K.H. 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.11

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

224-비트 소수체 타원곡선을 지원하는 공개키 암호 프로세서의 저면적 구현

박병관,신경욱,Park, Byung-Gwan,Shin, Kyung-Wook 한국정보통신학회 2017 한국정보통신학회논문지 Vol.21 No.6

NIST 표준에 정의된 소수체(prime field) GF(p) 상의 224-비트 타원곡선을 지원하는 타원곡선 암호 프로세서를 설계하였다. 타원곡선 암호의 핵심 연산인 스칼라 점 곱셈을 수정형 Montgomery ladder 알고리듬을 이용하여 구현하였다. 점 덧셈과 점 두배 연산은 투영(projective) 좌표계를 이용하여 연산량이 많은 나눗셈 연산을 제거하였으며, 소수체 상의 덧셈, 뺄셈, 곱셈, 제곱 연산만으로 구현하였다. 스칼라 점 곱셈의 최종 결과값은 다시 아핀(affine) 좌표계로 변환되어 출력하며, 이때 사용되는 역원 연산은 Fermat's little theorem을 이용하여 구현하였다. 설계된 ECC 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였다. $0.18{\mu}m$공정의 CMOS 셀 라이브러리로 합성한 결과 10 MHz의 동작 주파수에서 2.7-Kbit RAM과 27,739 GE로 구현되었고, 최대 71 MHz의 동작 주파수를 갖는다. 스칼라 점 곱셈에 1,326,985 클록 사이클이 소요되며, 최대 동작 주파수에서 18.7 msec의 시간이 소요된다. This paper describes a design of cryptographic processor supporting 224-bit elliptic curves over prime field defined by NIST. Scalar point multiplication that is a core arithmetic function in elliptic curve cryptography(ECC) was implemented by adopting the modified Montgomery ladder algorithm. In order to eliminate division operations that have high computational complexity, projective coordinate was used to implement point addition and point doubling operations, which uses addition, subtraction, multiplication and squaring operations over GF(p). The final result of the scalar point multiplication is converted to affine coordinate and the inverse operation is implemented using Fermat's little theorem. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 2.7-Kbit RAM and 27,739 gate equivalents (GEs), and the estimated maximum clock frequency is 71 MHz. One scalar point multiplication takes 1,326,985 clock cycles resulting in the computation time of 18.7 msec at the maximum clock frequency.

이웃 참조 위치가 없는 경우를 개선한 실내 위치 추정 사전 컷-오프 방식

박병관(Byoungkwan Park),김동준(Dongjun Kim),손주영(Jooyoung Son),최종민(Jongmin Choi) 한국멀티미디어학회 2017 멀티미디어학회논문지 Vol.20 No.1

이중 버퍼 제어기 구조의 터보 복호기를 사용한 전송률 가변 비대칭 TDD 시스템 설계

박병관(Byeung-Kwan Park),김미래(Mi-Rae Kim),김효종(Hyo-Jong Kim) 한국항공우주학회 2019 韓國航空宇宙學會誌 Vol.47 No.2

본 논문에서는 소형 무인기 데이터 링크 시스템에 적용이 가능한 전송률 가변 비대칭 TDD(Time Division Duplex) 방식에 대해 다루었다. 긴 복호 시간이 필요한 터보 복호기를 비대칭 TDD 방식에 적용하기 위하여 이중 버퍼 제어기 구조의 터보 복호기를 제안하였다. 제안 방법은 전송률 가변과 동일 송수신 시간에 최대의 데이터 전송이 가능하다. 제안 방식을 적용한 데이터 링크 시스템을 제작하여 성능을 확인하였다. 측정 결과, 대칭 TDD 방식에 비해 전송률은 최대 약 1.8배 증가하였다. PER(Packet Error Rate) 성능은 동일하며, 전송률 가변이 가능함을 확인하였다. This paper proposes a variable data transfer asymmetric TDD(Time Division Duplex) system for small UAV(Unmanned Aerial Vehicle) data link system. In the proposed method, a turbo decoder with a double buffer controller is proposed to apply turbo decoder with long decoding time to asymmetric TDD system. The proposed method achieves variable data transfer rate and maximum data transfer rate. The advantage of the proposed method is demonstrated by its data transfer rate. The measured data transfer rate is more than 1.8 times than that of symmetric TDD system. In addition, PER(Packet Error Rate) performance is the same and data transfer rate is variable.

Treatment of hydroponic wastewater by denitrification filter using plant prunings as the organic carbon source

박병관(J. B. K. Park),R. J. Craggs,J. P. S. Sukias 대한환경공학회 2006 대한환경공학회 학술발표논문집 Vol.2006 No.12

유동성 유지제 혼입율 변화에 따른 고성능 콘크리트의 기초적 특성

박병관(Park Byung-Kwan),노상균(Noh Sang-Kyun),백대현(Baek Dae-Hyun),裵長春(Pei Chang-Chun),한민철(Han Min-Cheol),한천구(Han Cheon-Goo) 대한건축학회 2008 대한건축학회 학술발표대회 논문집 - 계획계/구조계 Vol.28 No.1(구조계)

The study examined basic characteristics of fresh concrete and dynamic characteristics of hardening concrete followed by changes of mixing rate in fluidity-keeping agent as admixture to improve fluidity-keeping performance of high-performance concrete. There sults were as follows. Slump flow satisfied the scope of target in all mix proportions by design of mix proportion and its fluidity-keeping performance was better as the mixing rate of its keeping agent was increased irrespective of W /B, Air amount satisfied the scope of target in all mix proportions by design of mix proportion and all of the air amount followed by the diurnal variations irrespective of W IB was decreased. The setting time followed by each change of mixing rate in keeping agent was more delayed as W IB was higher and as the mixing rate of keeping agent was more increased. The setting time followed by change of curing temperature was more promoted as curing temperature was higher and was more decreased as the mixing rate of keeping agent was more increased. In changes of curing temperature, the early strength was more increased as curing temperature was higher and the early strength was similar irrespective of change of curing temperature in long-term age.