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Aqueous Extraction 공정을 이용한 난황에서의 콜레스테롤 분리
김일준(I . J . Kim),김영호(Y . H . Kim),김동훈(D . H . Kim),이무하(M . Lee) 한국축산학회 1996 한국축산학회지 Vol.38 No.5
The effect of the addition of com oil(10%, 20%, 30%, 40% and 50% of egg yolk weight) and bile salts(2.5%, 5%, 7.5%, 10%, 12.5% and 15% of egg yolk weight) on the separation of cholesterol from egg yolk was studied. The optimum aqucous extraction conditions used for the separation were obtained by the Response Surface method and included : the egg yolk dilution ratio of 1.5, 18.9% NaCl, pH of 6.6, temperature of 37.5℃. centrifugation speed of 35,000 rpm and centrifugation temperature of 15℃. When com oil was added up to 30%, the amount of Gel-type (G) and Oil (O) fractions decreased while the Aqueous (A) and Protein (P) fractions increased. This resulted in cholesterol separating into the A+P fractions rather than the G+O fractions. The formation of precipitate increased from the 5% level of bile salts. The decrease in the amount of cholesterol separated into the G+O fractions corresponded with the increase in precipitate. Therefore, com oil and bile salt did not seem to have a significant effect on the aqueous extraction of cholesterol from egg yolks. Under the same conditions the effect of protease was studied, showing that pH of 5.0, reaction temperature of 37.5℃, reaction time of 120 minutes and 50 U of enzyme/g egg yolk were the best for lipid separation. Considering these results along with previous reports, the following conditions were chosen for cholesterol separation from the egg yolk egg yolk dilution ratio of 4.0, pH of 5.0, 18.9% NaCl, reaction temperature of 37.5℃, reaction time of 120 minutes, 50 U enzyme/g of egg yolk, centrifugation speed of 45,000 rpm and temperature of 35℃. Ninety-seven percent of the cholesterol in the egg yolk was separated into the Gel-type oil fraction.
반응표면분석법을 이용한 난황에서의 콜레스테롤 분리를 위한 Aqueous Extraction 조건확립
김일준(I . J . Kim),김영호(Y . H . Kim),이성욱(S . W . Lee),이무하(M . Lee) 한국축산학회 1996 한국축산학회지 Vol.38 No.3
A response surface method with three reaction variables(pH, NaCl and temperature) was used to establish the optimum conditions for the aqueous extraction of cholesterol from egg yolk. Egg yolk was mixed with various NaCl solutions(concentrations, 0∼20%) in a ratio of 1 : 1.5(v/v), adjusted to various pHs(pH 4∼8) and then incubated for 5 minutes in a water bath at different temperatures (20∼60℃) with stirring. The egg yolk treated as above was centrifuged with 35,000 rpm at 15℃ for 4 hours to produce 4 fractions, from which the gel-type oil fraction and oil fraction, containing most of the egg yolk lipid, were analyzed for lipid, cholesterol and protein. From the response surface method, the optimum conditions for lipid separation was pH 6.60, 18.9% NaCl and temperature of 37.5℃ with the predicted yields of 79.9% lipid and 77.7% cholesterol. However, actual aqueous extraction under the optimum conditions resulted in lower separation with 71.88% lipid and 69.6% cholesterol than the theoretical values. Under the optimum conditions, the effects of egg yolk dilution ratio, centrifugation speed, centrifugation temperature, the addition of EDTA or stirring time on the cholesterol separation of the geltype oil fraction and oil fraction were investigated. The dilution ratio of 1:4, 45,000 rpm of centrifugation speed, and 25℃ centrifugation temperature were chosen as optimum conditions considering not only cholesterol but also protein fraction yield. The addition of EDTA or stirring time did not have any significant effect on the cholesterol separation.
김일준(RiJun Jin),박헌(Heon Park),하판봉(Pan-Bong Ha),김영희(Young-Hee Kim) 한국정보전자통신기술학회 2017 한국정보전자통신기술학회논문지 Vol.10 No.5
본 논문에서는 읽기 모드에서 BL (Bit Line)의 전압을 DL (Data Line)에 전달하는 시간을 줄이기 위해 기생하는 커패시턴스가 큰 distributed DB 센싱 방식 대신 기생하는 커패시턴스가 작은 local DL 센싱 방식을 제안하였다. 그리고 읽기 모드에서 NMOS 스위치를 빠르게 ON 시키는 BL 스위치 회로를 제안하였다. 또한 BL 노드 전압을 VDD-VT로 선 충전하는 대신 DL 클램핑 회로를 사용하여 0.6V로 클램핑 하고 차동증폭기를 사용하므로 읽기 모드에서 access 시간을 35.63ns로 40ns를 만족시켰다. 0.13㎛ BCD 공정을 기반으로 설계된 512Kb EEPROM IP의 레이아웃면적은 923.4㎛ × 1150.96㎛(=1.063㎟)이다. In this paper, a local DL (Data Line) sensing method with smaller parasitic capacitance replacing the previous distributed DB sensing method with large parasitic capacitance is proposed to reduce the time to transfer BL (Bit Line) voltage to DL in the read mode. A new BL switching circuit turning on NMOS switches faster is also proposed. Furthermore, the access time is reduced to 35.63ns from 40ns in the read mode and thus meets the requirement since BL node voltage is clamped at 0.6V by a DL clamping circuit instead of precharging the node to VDD-VT and a differential amplifier are used. The layout size of the designed 512Kb EEPROM memory IP based on a 0.13㎛ BCD is 923.4㎛ × 1150.96㎛ (=1.063㎟).
박헌(Heon Park),김일준(RiJun Jin),하판봉(Pan-Bong Ha),김영희(Young-Hee Kim) 한국정보전자통신기술학회 2017 한국정보전자통신기술학회논문지 Vol.10 No.2
대용량 EEPROM 메모리를 테스트하는 경우 erase time과 program time이 많이 걸리는 문제가 있다. 또한 신뢰성 테스트를 진행하면서 각 스텝마다 EEPROM 셀의 문턱전압 VT를 테스트할 필요가 있다. 본 논문에서는 512kb EEPROM 셀 검증용 모듈 회로를 설계하였으며, negative VTE를 갖는 split gate EEPROM의 VT 측정을 위한 CG(Control Gate) 구동회로를 제안하였다. 제안된 CG 구동회로는 erase VT를 측정하기 위해 -3V~0V의 negative 전압이 인가될 수 있도록 asymmetric isolated HV (High-Voltage) NMOS 소자를 사용하였다. 그리고 test time reduction 모드에서는 even page, odd page, chip 단위로 erase나 program 수행이 가능하도록 회로를 설계하므로 512Kb EEPROM 전체 메모리를 erase하거나 program할 때 시간을 even page와 odd page를 이용하는 경우는 4ms, chip 전체로 하는 경우는 2ms로 테스트 시간을 줄일 수 있었다. There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of .3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.
반응표면 분석법을 이용한 계란 난황 레시틴 분리 최적조건
장애라,임동균,전희준,조철훈,김일준,이무하,Jang, Ae-Ra,Lim, Dong-Gyun,Jeon, Hee-Joon,Jo, Cheo-Run,Kim, Il-Joon,Lee, Moo-Ha 한국축산식품학회 2007 한국축산식품학회지 Vol.27 No.4
난황으로부터 레시틴 고함유 인지질을 회수하기 위하여 전처리, 표면반응분석기법을 실시한 결과 난황 인지질 분리조건(난황액 100g 기준)은 알코올 농도 95.83%, 알코올 첨가량 1: 6.51, 균질온도 $40.2^{\circ}C$, 20,000 rpm에서 5분간 균질한 후 원심 분리하여 여과 후 진공농축하고 아세톤 150 mL로 1회 세척하여 분리한 것으로 수율은 인지질 64.8%이상 레시틴 함량 55.04%의 인지질 분리를 위한 공정을 확립하였다. The optimum conditions for the extraction of lecithin from egg yolk were determined using response surface methodology (RSM). On the basis of the results of preliminary experiments, the most effective values were selected. The effects of three independent variables, dilution ratio, solvent composition, and extraction temperature on the response of crude egg lecithin (g) were then determined. The optimum conditions for egg lecithin separation obtained using ridge analysis were 6.51, 95.83%, and $40.2^{\circ}C$ for the dilution ratio, solvent composition, and extraction temperature, respectively. Using the optimum conditions, 55.04% of crude lecithin in total phospholipid can be obtained from 100 g liquid egg yolk. The experimental values (56.21% crude lecithin in total phospholipid) agreed with the predicted values.
최대용(Cui Dayong),김일준(Jin Rijin),하판봉(Pang-Bong Ha),김영희(Young-Hee Kim) 한국정보전자통신기술학회 2016 한국정보전자통신기술학회논문지 Vol.9 No.4
본 논문에서는 저면적 64bit MTP IP를 설계하였다. 저면적 설계기술로는 MTP cell의 inhibit voltage를 기존의 VPP/3과 VNN/3 전압 대신 모두 0V를 사용하므로 VPPL(=VPP/3) regulator 회로와 VNNL(VNN/3) charge pump 회로를 제거하였다. 그리고 external pad를 이용하여 VPP program voltage를 forcing하므로 VPP charge pump 회로를 제거하였다. 또한 VNN charge pump는 VPP 전압을 이용하여 1-stage negative charge pump 회로로 pumping해서 -VPP의 전압을 공급하도록 설계를 하였다. 설계된 64bit MTP IP size는 377.585㎛ × 328.265㎛=0.124mm2)이며, DC-DC converter관련 layout size는 기존의 회로 대비 76.4%를 줄였다. In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of –VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip’s 0.18㎛ BCD process is 377.585㎛ × 328.265㎛ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.
딥러닝 기반 건축물 결함탐지 및 3차원 모델 내 위치 정량화
홍종화 ( Hong¸ Jonghwa ),김일준 ( Kim¸ Iljun ),심성한 ( Sim¸ Sung-han ) 한국구조물진단유지관리공학회 2023 한국구조물진단유지관리공학회 학술발표대회 논문집 Vol.27 No.2
현행 법령의 의무관리 대상에서 제외된 30년 이상 중소규모 다중이용 노후건축물 수는 총 47만동으로 최근 큰 사회적 이슈를 야기하고 있으며, 체계적이고 정확한 노후건축물 안전점검은 안전사고와 인명 피해를 예방하기 위한 필수적인 조치로 인식되고 있다. 기존 노후건축물 안전점검은 인력에 의한 육안점검 방식으로 이루어지고 있고 이는 막대한 인력과 예산, 기간이 소요되기 때문에 효율적이고 체계적인 안전점검 수행이 어렵다. 이러한 이슈를 해결하기 위해 본 연구에서는 드론으로 노후건축물의 외관 영상을 촬영하고, 딥러닝 기반 결함탐지 자동화와 탐지된 결함의 3차원 모델 내 위치를 정량화하는 방법을 제안한다.