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CSL-NOR형 SONOS 플래시 메모리의 멀티비트 적용에 관한 연구
김주연,안호명,이명식,김병철,서광열,Kim Joo-Yeon,An Ho-Myoung,Lee Myung-Shik,Kim Byung-Cheul,Seo Kwang-Yell 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.3
NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.
테라비트급 나노 스케일 SONOS 플래시 메모리 제작 및 소자 특성 평가
김주연,김문경,김병철,김정우,서광열,Kim, Joo-Yeon,Kim, Moon-Kyung,Kim, Byung-Cheul,Kim, Jung-Woo,Seo, Kwang-Yell 한국전기전자재료학회 2007 전기전자재료학회논문지 Vol.20 No.12
To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.