적극적 전력 관리를 위한 ACPI 확장

황영시(Youngsi Hwang),김원진(Wonjin Kim),정찬민(Chanmin Jung),정기석(Kiseok Chung) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11

Embedded OS-directed power management techniques have gained lots of attention lately. Because the OS has the manager of the overall system operation, and has the exact information of the running system. Power management by the OS may have great impact for the optimization of the power consumption. The ACPI (Advanced Configuration and Power Interface) is an open industry specification co-developed by Intel, Microsoft, and Toshiba that defines a flexible and extensible interface for power management in PCs and related hardware. Since the ACPI lias been proposed for the desktop PC, it is not sufficient to aggressively manage the power mode for embedded systems. Therefore, we implement E-ACPI, an extended ACPI which is designed for an advanced power management of embedded systems. In this paper, we address (ⅰ) how we extend the exiting ACPI to E-ACPI, (ⅱ) technical challenges to overcome in implementation, and (ⅲ) how we port our E-ACPI to an embedded linux system in this paper. Experimental results show that our E-ACPI is very useful and effective in practice.

E-ACPI : 임베디드 시스템에서 적극적 전력 관리를 위한 전력관리 인터페이스 구현

황영시(Young-Si Hwang),정기석(Ki-Seok Chung) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.3

운영체제 수준의 전력 소모 최적화 기법에 대한 관심이 고조되고 있다. 운영체제는 시스템의 실행에 있어 종합적인 관리를 하기 때문에 시스템의 전력 소모에 막대한 영향을 미칠 수 있고, 이에 따라 전력 소모를 고려한 운영체제(Power Aware OS)에 대한 관심이 매우 높아지고 있다. 마이크로소프트, 인텔, 도시바 등의 회사에서 공동으로 제정한 ACPI 표준은 다양한 장치들의 전력관리를 BIOS/Firmware 수준이 아닌 운영체제 수준에서 효과적으로 고급 기법을 적용할 수 있도록 한다는 점에서 매우 효용성이 높은 것으로 평가 받고 있다. 본 논문에서는 데스크탑, 노트북 플랫폼 기반의 ACPI를 임베디드 리눅스 시스템에 구현한 포팅 방법에 대하여 설명한다. 또한 구현 과정 중에 극복되어 왔던 기술적인 측면들에 대하여 고찰한다. The OS has the manager of the overall system operation, and has the exact information of the running system. Power management by the OS may have great impact for the optimization of the power consumption. We implement E-ACPI, an extended ACPI which is designed for an advanced power management of embedded systems. In this paper, we address (ⅰ) how we extend the exiting ACPI to E-ACPI, (ⅱ) technical challenges to overcome in implementation, and (ⅲ) how we port our E-ACPI to an embedded linux system in this paper. Experimental results show that our E-ACPI is very useful and effective in practice.

멀티코어 환경에서 커널 수준의 전력 관리 솔루션

안영호,황영시,정기석,Ahn, Youngho,Hwang, Young-Si,Chung, Ki-Seok 대한임베디드공학회 2009 대한임베디드공학회논문지 Vol.4 No.2

In this paper, we address a novel system-level power management technique which is specifically targeted for an ARM 11 MPCore system. Our proposed solution is a DPM technique which includes process monitoring, real time power analysis, and policy application to reduce the power consumption while meeting the performance requirement. One of the main contributions of this paper is that we systematically infer QoS requirements of processes without getting any additional information from the application. When multiple processes are running under various user level policies, priorities of the policy application are determined in such a way that the overall system performance is maintained while power consumption is effectively managed. Experimental results show that our DPM technique is very effective in reducing power consumption without violating system's QoS requirements.

Network-on-Chip에서의 최적 통신구조 설계

윤주형,황영시,정기석,Yoon, Joo-Hyeong,Hwang, Young-Si,Chung, Ki-Seok 대한전자공학회 2007 電子工學會論文誌-SD (Semiconductor and devices) Vol.44 No.8

매우 복잡한 시스템의 보다 효율적인 설계를 위한 차세대 SoC를 위해 중요한 것은 시스템의 고적용성과 고확장성이다. 이를 위해 최근 들어 급속히 관심이 높아지는 것이 계산 모듈중심의 시스템 설계를 탈피하여 통신 중심으로 시스템 설계를 보는 communication-based 설계 방법론이며, 그 중 대표적으로 많은 관심을 모으고 있는 것이 Network-on-Chip (NoC)이다. 이는 모듈간의 직접적인 연결에 의한 데이터의 통신 구조를 가진 일반적인 SoC 설계에서의 취약한 확장성과 통신 구조의 고정성을 극복하기 위해, 데이터를 패킷화하고, 이를 네트워크 인터페이스 및 라우터에 의한 가변적인 구조에 의해 전송함으로써 통신 구조의 적용성과 확장성을 제공하려는 노력이다. 하지만 확장성과 적용성에 치중하다 보면 성능과 면적에 대한 비용이 너무 커져서 실제로 기존의 연결 방법과 비교하여 실용성이 없을 수 있다. 그래서 본 연구에서는 통신 패턴의 면밀한 분석을 통하여 매우 성능에 중요하고 또 빈번한 통신 패턴에 대해서는 기존의 연결 방식을 고수하면서, 전체적인 연결성 및 확장성을 유지하는 알고리즘을 제시한다. 이 방법을 통해서 최소 30%의 네트워크 인터페이스 및 라우터 구조가 훨씬 간단한 구조로 바뀔 수 있었으며, 이로 인한 연결성 (connectivity) 및 확장성에 대한 손실은 거의 없었다. 시뮬레이션 결과에 의하면 통신 구조의 최적화를 통해서 연결에 소요되는 시간적 성능은 49.19% 향상되었고 면적의 측면에서도 24.03% 향상되었음이 입증되었다. High adaptability and scalability are two critical issues in implementing a very complex system in a single chip. To obtain high adaptability and scalability, novel system design methodology known as communication-based system design has gained large attention from SoC designers. NoC (Network-on-Chip) is such an on-chip communication-based design approach for the next generation SoC design. To provide high adaptability and scalability, NoCs employ network interfaces and routers as their main communication structures and transmit and receive packetized data over such structures. However, data packetization, and routing overhead in terms of run time and area may cost too much compared with conventional SoC communication structure. Therefore, in this research, we propose a novel methodology which automatically generates a hybrid communication structure. In this work, we map traditional pin-to-pin wiring structure for frequent and timing critical communication, and map flexible and scalable structure for infrequent, or highly variable communication patterns. Even though, we simplify the communication structure significantly through our algorithm the connectivity or the scalability of the communication modules are almost maintained as the original NoC design. Using this method, we could improve the timing performance by 49.19%, and the area taken by the communication structure has been reduced by 24.03%.

한국 노인의 사회경제적 취약과 인지기능장애의 상관관계

박상균(Sang Kyun Park),황영시(Young Si Hwang),오병택(ByungTaek Oh),이준영(Jun Young Lee),홍승완(Seung Wan Hong),김성희(Sung Hi Kim),김대현(Dae Hyun Kim) 대한임상노인의학회 2017 대한임상노인의학회지 Vol.18 No.2

Background: The relationship between socioeconomic status and cognitive dysfunction is still unknown. The aim of this study is to determine the relationship between cognitive impairment and socioeconomic vulnerability on elderly people in Korea by Korean Longitudinal Study on Aging (KLoSA). Methods: Authors collected data from Korean Longitudinal Study on Aging (KLoSA). Cognitive function was assessed by the Korean version of the mini-mental state examination-Korea (MMSE-K). And, the authors created the socioeconomic vulnerability (SEV) score, consisted of 6 items. Those 6 items are education level, house income, social engagement score, self-related economic satisfaction percentage, private insurance and residence. Results: A total of 4,044 participants were included and 2,045 subjects were classified as cognitive impaired whose MMSE is lower than 23. SEV score was significantly different between normal and cognitive impairment group. Authors divided four SEV groups by SEV severity. Increased SEV score was significantly correlated with cognitive impairment group (Odds ratio SEV Q2: 2.84, Q3: 5.69 and Q4:10.67). In addition, diabetes mellitus (1.29, 1.06∼1.61), depression (1.23, 1.04∼1.46), function (ADL: 2.48, 1.61∼3.82, IADL: 1.95, 1.54∼2.47) also correlated with cognitive impairment. Conclusion: Socioeconomic vulnerability was strongly correlated with cognitive impairment. Depression, diabetes and independent functionality (ADL, IADL) were also significant correlated with cognitive impairment.

한국 노인에서 악력 저하와 관련된 요인

오병택(Byung Taek Oh),황영시(Young Si Hwang),이준영(Jun Young Lee),박상균(Sang Kyun Park),홍승완(Seung Wan Hong),서영성(Young Sung Suh),김대현(Dae Hyun Kim) 대한임상노인의학회 2017 대한임상노인의학회지 Vol.18 No.1

Background: Hand grip strength is important to identify old people with functional limitation. The objective of this study was to investigate the factors related with Reduction of Hand grip strength in Korean elderly. Methods: Korean community-dwelling elderly (n=3,598, male/female 1,577/2,021) at the first wave (2006) of KLoSA (Korean Longitudinal Study on Aging) were used for analysis. Hand grip strength was assessed with Dynamometer for 2times each arm and we calculated hand grip index. Hand grip strength, Socioeconomic status, Health related status was assessed through personal interviews by a trained interviewer with Computer Assisted Personal Interviewing (CAPI). Results: 1,684 subjects (46.8%) were classified as Low hand grip strength group (<26 kg for male, <18 kg for female). Age, sex, MMSE score, education, employment, living with spouse, social activity, depression scale (Center for epidemiologic studies depression scale, CESD-10), function (Activity of daily living, ADL), smoking, drinking, BMI (Body mass index), hypertension and diabetes was significantly related with low hand grip strength. Low hand grip strength ratio for age 70∼74 and ≥75 were 1.68 (1.40∼2.02) and 2.89 (2.39∼3.50) compare to younger age group, female was 2.04 (1.73∼2.40), cognitive impairment was 1.84 (1.57∼2.16), no exercise group was 1.34 (1.13∼1.58). Among health-related factors, alcohol consumption and diabetes were significantly higher in low grip strength group. Among physical/psychological factors, cognitive impairment (MMSE≤23), function (ADL), depression scale (CESD-10), obesity were significantly different after multivariates adjustment. Conclusion: Age, sex, education, employment, alcohol consumption, diabetes, cognitive impairment, depression scale (CESD-10), function (ADL), exercise, obesity were significantly related with cognitive decline in Korean elderly.

전력소모 민감도와 실행시간 불확실성을 고려한 동적 전압 조절 기법

정기석(Ki-Seok Chung),황영시(Young-Si Hwang) 한국정보과학회 2006 정보과학회지 Vol.24 No.8

임베디드 시스템의 가상 ARM 머신의 개발

이소진,안영호,한현희,황영시,정기석,Lee, So-Jin,An, Young-Ho,Han, Alex H,Hwang, Young-Si,Chung, Ki-Seok 대한임베디드공학회 2008 대한임베디드공학회논문지 Vol.3 No.1

To reduce time-to-market, more and more embedded system developers and system-on-chip designers rely on microprocessor-based design methodology. ARM processor has been a major player in this industry over the last 10 years. However, there are many restrictions on developing embedded software using ARM processor in the early design stage. For those who are not familiar with embedded software development environment or who cannot afford to have an expensive embedded hardware equipment, testing their software on a real ARM hardware platform is a challenging job. To overcome such a problem, we have designed VMA (Virtual ARM Machine), which offers easier testing and debugging environment to ARM based embedded system developers. Major benefits that can be achieved by utilizing a virtual ARM platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. Unlike many other purely software-oriented ARM simulators which are independent of real hardware platforms, VMA is specifically targeted on SYS-Lab 5000 ARM hardware platform, (designed by Libertron, Inc.), which means that VMA imitates behaviors of embedded software as if the software is running on the target embedded hardware as closely as possible. This paper will describe how VMA is designed and how VMA can be used to reduce design time and cost.

응용 프로그램의 특성 반영이 가능한 트래픽 생성기

여필구(Phil-koo Yeo),조걸(Keol Cho),유대철(Dae-chul Yu),황영시(Young-si Hwang),정기석(Ki-seok Chung) 大韓電子工學會 2011 電子工學會論文誌-SD (Semiconductor and devices) Vol.48 No.9

다양한 컴포넌트의 집적과 저전력 정책에 대한 연구가 활발했던 시스템 온 칩 설계 분야에서는 최근 들어 집적되는 컴포넌트의 수가 늘어나고 특성이 다양해짐에 따라 이들의 인터커넥션 문제가 새로운 이슈로 주목받고 있다. 시스템 온 칩이 주목받기 시작한 이후로 컴포넌트들의 구성에 따른 성능을 평가하기 위한 각종 시뮬레이터의 개발이 진행되어 왔으며, 효율적인 컴포넌트간의 인터커넥션 설계를 위한 시뮬레이션 환경도 개발이 진행되어 이들을 이용한 성능 평가가 실제 설계에 반영되고 있다. 대부분의 시뮬레이션 환경은 시스템 온 칩의 성능을 테스트하는 데 있어서 수학적 확률 함수를 기반으로 한 트래픽을 사용하고 있으나, 이는 실제 칩의 동작을 테스트하기에는 한계가 있다. 따라서 실질적인 칩의 테스트를 위하여 시스템 상에서의 동작을 정확하게 모사할 수 있는 시뮬레이터의 필요성이 고조되고 있으나, 실제로 이러한 트래픽 생성 방법을 적용한 시뮬레이터는 전무한 실정이다. 이에 본 논문에서는 멀티 프로세서 시스템 온 칩 상에서 수학적 확률 모델은 물론 실제 시스템의 동작을 모사하는 시뮬레이션이 가능한 트래픽 생성 방법을 제안한다. 본 논문에서 제안된 트래픽 생성법은 실제 응용프로그램의 특성을 반영할 수 있도록 트래픽을 생성하므로 수학적 확률 함수를 이용한 트래픽 생성법보다 실제 동작에 가까운 시뮬레이션을 진행할 수 있으며 이는 인터커넥션에 따른 시스템의 성능을 실효적으로 비교할 수 있는 환경을 제공한다. 본 논문에서는 시뮬레이션을 통해 제안된 트래픽 생성법과 수학적 확률 함수를 이용한 트래픽 생성법의 차이를 비교하여 제안된 생성법의 이점에 대해 알아본다. Integrating massive components and low-power policies have been actively investigated for system-on-chip designs. But in recent years, finding the optimal interconnection structure among heterogeneous components has emerged as a critical system design issue. Therefore, various simulation tools to model interconnection designs are being developed and performance evaluation of simulation is reflected in the real design. But most of the simulation environments employ traffic generation based on the mathematical probability functions, and such traffic generation cannot fully cover for various situations that may be occurred in the real system. Therefore, the demand for traffic pattern generation based on real applications is increasing. However, there have been few simulators that adopt application-specific traffic generators. This paper proposes a novel traffic generation method in simulating various interconnection structures for multi-processor system-on-chip design. The proposed traffic generation method can generate traffic patterns that can reflect the actual characteristics of the application and evaluate the performance of an interconnection structure under more realistic circumstance than traffic patterns using mathematical probability functions. By comparing the differences between the proposed method and the one based on mathematical probability functions, this paper shows advantages of the proposed traffic generation method.