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조경연 ( Cho Gyung Yun ) 한국정보처리학회 1996 정보처리학회논문지 Vol.3 No.5
The increase of additional information broadcasting of TV demands a graphic overlay processor. This paper is about the design, implementation and testing of a graphic overlay processor called by KBPS decoder ASSP(Application Specific Standard Product) which is compliance with Korea Broadcast Programming System. KBPS decoder ASSP consists of embedded 8 bit microprocessor Z80, graphic overlay controller, KBPS schedule decoder, memory controller, priority interrupt controller, MIDI controller, infrared remocon receiver, asyncserial communication controller, timer, bus controller, universal parallel input-output port and serial-parallel interface. The 0.8 micron CMOS Sea of Gate is used to implement the ASSP in amount of about 31,500 gates, and it is running at 14.318MHz.
한국어 정보처리 : 니블 RLE 코드에 의한 비트 맵 데이타의 압축과 복원에 관한 연구
조경연(Cho Gyung Yun) 한국정보처리학회 1995 정보처리학회논문지 Vol.2 No.6
본 논문에서는 한글 비트 맵 폰트와 프린터 데이타의 실시간 압축과 복원에 적합한 니블 RLE(Run Length Encoding)코드를 제안한다. 제안한 코드를 명조체와 고딕체 완성형 한글 폰트와 프린터 출력 데이타에 적용하여 압축율이 좋음을 보인다. 그리고 압축과 복원을 분리하여 각각 하나의 ASIC(주문형 반도체)으로 설계하고 CAD상에서 시뮬레이션하여 동작을 확인한다. ASIC은 0.8 미크론 CMOS 게이트 어레이로 설계하여 약 2,400 게이트가 소요되었으며 25MHz 클럭으로 동작하였다. 따라서 제안한 코드는 간단한 하드웨어로 최고 100M bit/sec로 압축 및 복원을 수행하여 실시간 응용에 적합하다. In this paper, a nibble RLE(Run Length Encoding) code for real time compression and decompression of Hanguel bit map font and printer data is proposed. The nibble RLE code shows good compression ratio in complete form Hangeul Myoungjo and Godik style bit map font and printer output bit map data. And two ASICs seperating compression and decompression are designed and simulated on CAD to verify the proposed code. The 0.8 micron CMOS Sea of Gate is used to implement the ASICs in amount of 2,400 gates, and these are running at 25MHz. Therefore, the proposed code could be implemented with simple hardware and performs 100M bit/sec compression and decompression at maximum, it is good for real time applications.
박화식(Park Hwa Sik),조경연(Cho Gyung Yun) 한국정보처리학회 1998 정보처리학회논문지 Vol.5 No.2
In this paper, a new Huffman encoding algorithm with memory based Huffman table is proposed. The memory based table on the Huffman code of the canonical tree form consists of the Run-length code of the consecutive '1's and the rest of the code bit stream. The proposed algorithm is suitable for the hardware implementation since the construction of the table is simple and the encoding process is operated by only performing Run-length decoding and shift operation. The proposed encoder is implemented by using VHDL. simulated and verified the operation on the COMPASS. The designed chip occupies about 5,000 gates using 0.8 micron process. It is normally simulated at the 25 MHz clock. The proposed Huffman encoder is expected that it will be widely applied to the real-time processing such as the field of multimedia, digital data communications, since it is suitable for the hardware implemention.
조경연,허웅,이주근 명지대학교 대학원 1989 明知大學校開校四十周年記念論文集 Vol.1989 No.-
In this paper, we propose the architecture of the SPDRAM(Single Port Dual RAM) which is a hierarchical memory device containing both SRAM and DRAM. At the conventional cache design, to get the marits of high integration of DRAM and of high speed of SRAM, both of SRAM and DRAM are used by the external placement. So, it results in no good performance due to narrow data transfer width. To overcome this drawback of conventional cache, the proposed SPDRAM has a SRAM cell which works by the unit of a word line between DRAM sense amp and I/O data gate. This architecture can enlarge the data transfer width. This SPDRAM also eliminates the overlapped circuits of SRAM and DRAM. That enhances the integration degree and gives the versatile functions with new control scheme. The SPDRAM fits into high performance memory system like computer. And also it allows to make various kinds of SPDRAM and to expend to 4 Mbit and 16 Mbit ones.
조경연,허웅,이주근 명지대학교 대학원 1989 明知大學校開校四十周年記念論文集 Vol.1989 No.-
This paper proposes a hierarachical bit line structure containing both of SRAM and DRAM. The hierarchical bit line consists of DRAM cell, DRAM sense amp, interface gate, SRAM cell and other auxiliary circuits. It functions with high versatility, which adpots well into computer memory. And also, the extended hierarchical bit line which is the extended one of the hierarchical bit line can mark the mapping of memory system in a good efficient way at on-chip. The proposed bit lines are simulated with SPICE to conform their operations.