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차충현(C. H. Cha),심현철(H. C. Shim),전석희(S. H. Jeon),유종근(C. G. Yu) 대한전기학회 2007 대한전기학회 학술대회 논문집 Vol.2007 No.10
In this paper, a 10Gb㎰ Clock and Data Recovery circuit is designed in 0.18㎛ CMOS Technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a Charge Pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.1㎰ and a peak-to-peak recovered data jitter of 8㎰ while consuming about 44㎽ from a I.8V supply.
UHF 대역 RFID Tag용 저전력 아날로그 회로 설계
심현철(H. C. Shim),박종태(J. T. Park),유종근(C. G. Yu) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
This paper describes a low-power analog front-end block for UHF(860~960㎒) band RFID tags. It satisfies ISO/IEC 18000-6 type C(EPCgolbal class1. generation2.) and operates with an internally generated power supply of 1V. It contains a rectifier, a voltage regulator, an ASK demodulator, a bandgap reference, a clock generator, a power-on-reset circuit, and a backscatter modulator. It is designed using a 0.18㎛ CMOS technology. The simulation results show that the designed circuit can operate properly with an input as low as 0.2Vpeak and consumes 25.2㎂.
2.5㎓ 0.25㎛ CMOS Dual-Modulus 프리스케일러 설계
오근창(K. C. Oh),강기섭(K. S. Kang),박종태(J. T. Park),유종근(C. G. Yu) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.10
A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a 0.25㎛ CMOS process. In the design a new dynamic Dr-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates UP to 2.5㎓ and consumes 3.1㎃ at 2.5㎓ operation.
0.18um CMOS 공정을 이용한 UHF 대역 RFID 태그 칩 설계
김도희(D. H. Kim),송준호(J. H. Song),조영호(Y. H. Cho),고승오(S. O. Ko),유종근(C. G. Yu) 대한전기학회 2008 대한전기학회 학술대회 논문집 Vol.2008 No.10
본 논문에서는 UHF 대역 RFID의 국제표준인 ISO/IEC 18000-6C 표준을 만족하는 태그 칩을 위한 저전력 고성능 아날로그 회로를 설계 하였다. 설계된 아날로그 회로는 성능 테스트를 위해 메모리 블록을 포함하고 있으며, 태그의 인식률과 경제성을 위해 저전력 및 칩 면적의 최소화에 중점을 두고 설계하였다. 설계된 UHF 대역 RFID 태그용 아날로그 회로는 0.24Vpeak의 RF 입력으로 동작이 가능하며, 칩 면적은 552.5㎛ ×338.8㎛로, UHF 대역 RFID 태그칩에 적합한 작은 면적을 갖는다.
박준규(J. K. Park),심현철(H. C. Shim),박종태(J. T. Park),유종근(C. G. Yu) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.10
This paper describes a 2.5V, 320㎒ low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25㎛ CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7㎒-670㎒. The oscillator consumes 1.58㎃ from a 320㎒ frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320㎒, the jitter and phase noise measured 26㎰ (rms), 157㎰ (p-p) and -97.09㏈ at 100㎑ offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.
UHF 대역 RFID 리더 응용을 위한 주파수합성기 설계
김경환(K. H. Kim),오근창(K. C. Oh),박동삼(D. S. Park),유종근(C. G. Yu) 대한전기학회 2007 대한전기학회 학술대회 논문집 Vol.2007 No.10
This paper presents a 900㎒ fractional-N frequency synthesizer for radio frequency identification (RFID) reader using 0.18㎛ standard CMOS process. The IC meets the EPC Class-1 Generation-2 and ISO-18000 Type-C standards. To minimize VCO pulling, the 900㎒ VCO is generated by a 1.8㎓ VCO followed by a frequency divider. The settling time of the synthesizer is less than 20㎛. The frequency synthesizer achieves the phase noise of -105.6㏈c/㎐ at 200㎑ offset. The frequency synthesizer occupies an area of 1.8 × 0.99㎟, and dissipates 8㎃ from a low supply voltage of 1.8V.
DTV 튜너 응용을 위한 광대역 저잡음 CMOS VCO 설계
김용정(Y. J. Kim),유지봉(J. B. Yu),고승오(S. O. Ko),김경환(K. H. Kim),유종근(C. G. Yu) 대한전기학회 2007 대한전기학회 학술대회 논문집 Vol.2007 No.10
Since the digital TV signal band is very wide (54~806㎒), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18㎛ CMOS process consists of a wideband LC VCO, five divide-by-2 circuits and several buffers. The simulation results show that the designed circuit has a phase noise at 10㎑ better than -87㏈c/㎐ throughout the signal band and consumes 10㎃ from a 1.8V supply.
MB-OFDM UWB 시스템을 위한 주파수 합성기의 유형별 설계 및 비교
이재경(J. K. Lee),정태현(T. H. Cheong),박종태(J. T. Park),유종근(C. G. Yu) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.10
This paper describes fast-hopping frequency synthesizers for multi-band OFDM(MB-OFDM) ultra-wide band(UWB) systems. Three different structures in generating 3 center frequencies(3432㎒, 3960㎒. 4488㎒) are designed and compared. The first structure generates 3 center frequencies using only one PLL operating at 4224㎒. The second uses three PLLs operating at corresponding center frequencies. The third employes two PLLs operating at 3960㎒ and 528㎒. Simulation results using a 0.18㎛ RF CMOS process parameters show that the third structure exhibit the best characteristics. The band switching time of the proposed synthesizer is less than 1.3㎱ and the spur is less than -36㏈c. The synthesizer consumes 22㎃ from a 1.8V supply.