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Latchup이 발생하지 않는 Trench-Isolated CBiCMOS 소자의 설계
송인채 崇實大學校 生産技術硏究所 1998 論文集 Vol.28 No.-
We desined latchup-free CBICMOS devices which operate at high speech even if scaling down. We adopted trench isolation technogy, which allows high integrity and low capacitance. According to simulation results, current gaing and cutoff frequency of the NPN transistor are 200 and 22 GHz, respectively, and those of the PNP transistor are 35 and 10 GHz, respectively. The transconductance of the NMOS transistor with the channel length of 1.5 ㎛ and the gate oxide of 300Å is 6.02x10-?? A/㎛V, and that of the PMOS transistor is 2.16x10-??A/㎛V. We found out that the designed devices were free from latchup if the epitaxial layer thickness is less than 9㎛ with the p+ substrate.
송인채 崇實大學校 生産技術硏究所 1995 論文集 Vol.25 No.1
A mathematical model for the Varian 3125 sputter deposition system has been developed to investigate step coverage profile. The model is a generalized on which can be extended to any other sputtering deposition system. The step coverage of TaSi₂on polysilicon has been simulated and compared with experimental observation by SEM(Scanning Electron Microscopy), which shows good agreement. Simulation results show that step coverage depends on step shape, step orientation, and the ratio of the film thickness to the step height. Step coverage can be optimized by shaping the step properly such as rounding the corner and varying the slope.
송인채 崇實大學校 生産技術硏究所 1993 論文集 Vol.23 No.-
We propose to substantially improve the dc-to-RF conversion efficiency of the quantum well injection transit time (QWITT) diode by introducing a compositionally graded drift region. The built-in effective electric field due to the conduction band grading allows us to reduce dc bias voltage, and consequently enhances the efficiency. Simulations of the proposed structure have been carried out using energy-band parameter of the AlGaAs system. The conversion efficiency is found to be increased by more than one third throughout the millimeter-wave frequency range.
송인채 崇實大學校 1999 論文集 Vol.29 No.1
The performance of electronic devices is degraded when exposed to radiation environment. We investigated radiation effects on common-emitter current gain which is one of the most important parameters of bipolar devices. Employing a two-dimensional device simulator, the simulation results show a good agreement with the experimental results. In this simulation, we introduced surface recombination at the interface between silicon and silicon dioxide.
속도 오버슈트 효과를 이용하여 서브밀리미터파 주파수 영역에서 동작하는 주행 시간 다이오드
송인채 대한전자공학회 2002 電子工學會論文誌-SD (Semiconductor and devices) Vol.39 No.10
We propose a new transit time device to extend the operating frequency to submillimeter-wave (extreme infrared) ranges by utilizing velocity overshoot effects in the drift region. We name it a velocity overshoot transit time (VOTT) diode. This device adopts fast heterostructure tunneling as injection mechanism and a short drift region to optimize the velocity overshoot effects. To enhance dc-to-RF conversion efficiency, the drift region is designed with a bandgap grading method. Simulation results demonstrate that a VOTT diode can be operated at THz ranges. 드리프트 영역에서의 속도 오버슈트 효과를 이용하여 서브밀리미터파 주파수 영역에서 동작하는 새로운 주행 시간 소자를 제안한다. 이 소자를 속도 오버슈트 주행 시간 (VOTT) 다이오드라 명명한다. 이 소자는 캐리어 주입 메커니즘으로 빠르게 이루어지는 이종구조 터널링을 이용하며, 속도 오버슈트 효과를 최적화하기 위하여 짧은 드리프트 영역을 갖는다. 변환효율을 증대시키기 위하여 에너지 대역 간극을 경사시키는 방법으로 드리프트 영역을 설계한다. 모의실험결과에 따르면 이 소자는 THz 영역에서 동작하리라 기대된다.
Wallace 트리 기법을 이용한 8x8비트 곱셈기의 설계
이재규,송인채,최용석 崇實大學校 生産技術硏究所 1996 論文集 Vol.26 No.1
In this paper, we designed and fabricated an 8 x 8 bit multiplier with 0.8㎛ double-level metal CMOS technology. To improve calculation time, we adopted Wallace tree arrays using 4 : 2 compressor units and a 16-bit carry-lookahead adder(CLA) composed of four 4-bit CLAs. The number of propagation stages in the array could be reduced by galf using 4 : 4 compressors. In the last propagation stage, we used CLAs to add suums and carries coming the Wallace tree arrays. This multiplier contains about 3200 transistors in the area of 2.5 mm x 2.2 mm. It operates at 50MHz according to the test.
박성진,송인채 崇實大學校 生産技術硏究所 2001 論文集 Vol.31 No.-
In this paper, we designed a turbo decoder with constraint length v = 4, code rate R = 1/3, Generator polynomial G = (13, 15)_8 and 192-bit block size using VHDL. This decoder makes use of 3-bit soft decision. A systematic recursive convolutional encoder was used for a turbo encoder. We employed MAP(maximum a posteriori) algorithm for the decoder. A MAP decoder is more suitable for iterative error correction code compared with a SOVA (soft output Viterbi algorithm) decoder. To maximize effective free distance of the turbo code, we employed pseudo random interleaver and deinterleaver. In order to improve BER (bit error rate), iteration algorithm was used. We avoided multiplication by using lookup tables. We simulated the turbo decoder with Altera MAX+PLUSⅡ.