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ULSI DRAM의 BIST 알고리즘을 위한 제어회로 설계
온정근,김대익,도경주,이영훈,이창기,전병실 전북대학교 전자산업개발연구소 1991 전자산업연구 Vol.2 No.-
Lately, more developed semiconductor technolgy is, higher integration per one chip is rapidly. Mow 64 Mb DRAM is used 0.3㎛ techonology. This very large integration is caused faults of new type, and exhaused much time for test. So algorithms which distiguish at higher faults coverage. less time and cost of test is reported. In this paper control circuit of Built-In Self Test(BIST) Algorithm was designed for ULSI DRAM and simulated with MYCAD. This control circuit is carried out steps of algorithm, controlled generation of test patterns and data, generated control signals of parallel test.
ULSI DRAM의 BIST 알고리즘을 위한 패턴발생회로 설계
온정근,김대익,도경주,이영훈,이창기,전병실 전북대학교 전자산업개발연구소 1991 전자산업연구 Vol.2 No.-
Lately, more developed semiconductor technolgy is, higher integration per one chip is rapidly. Mow 64 Mb DRAM is used 0.3㎛ techonology. This very large integration is caused faults of new type, and exhaused much time for test. So algorithms which distiguish at higher faults coverage. less time and cost of test is reported. In this paper control circuit of Built-In Self Test(BIST) Algorithm was designed for ULSI DRAM. This circuit generates patterns of the algorithm by input clocks.