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4H-SiC PiN과 SBD 다이오드 Deep level trap 비교 분석
구상모,신명철,변동욱,이건희,신훈규,이남석,김성준 한국반도체디스플레이기술학회 2022 반도체디스플레이기술학회지 Vol.21 No.2
We investigated deep levels in n-type 4H-SiC epitaxy layer of the Positive-Intrinsic-Negative diode and Schottky barrier diodes by using deep level transient spectroscopy. Despite the excellent performance of 4H-SiC, research on various deep level defects still requires a lot of research to improve device performance. In Positive-Intrinsic-Negative diode, two defects of 196K and 628K are observed more than Schottky barrier diode. This is related to the action of impurity atoms infiltrating or occupying the 4H-SiC lattice in the ion implantation process. The I-V characteristics of the Positive-Intrinsic-Negative diode shows about ~100 times lower the leakage current level than Schottky barrier diode due to the grid structures in Positive-Intrinsic-Negative. As a result of comparing the capacitance of devices diode and Schottky barrier diode devices, it can be seen that the capacitance value lowered if it exists the P implantation regions from C-V characteristics.
3.3kV SiC MOSFET 설계 및 제작을 위한 JFET 및 FLR 최적화 연구
구상모,강예환,이현우 한국반도체디스플레이기술학회 2023 반도체디스플레이기술학회지 Vol.22 No.3
The potential performance benefits of Silicon Carbide(SiC) MOSFETs in high power, high frequency power switching applications have been well established over the past 20 years. In the past few years, SiC MOSFET offerings have been announced by suppliers as die, discrete, module and system level products. In high-voltage SiC vertical devices, major design concerns is the edge termination and cell pitch design Field Limiting Rings(FLR) based structures are commonly used in the edge termination approaches. This study presents a comprehensive analysis of the impact of variation of FLR and JFET region on the performance of a 3.3 kV SiC MOSFET during. The improvement in MOSFET reverse bias by optimizing the field ring design and its influence on the nominal operating performance is evaluated. And, manufacturability of the optimization of the JFET region of the SiC MOSFET was also examined by investigating full-map electrical characteristics.
구상모,최창용,조원주,김상식,Qiliang Li,John S. Suehle,Curt A. Richter,Eric M. Vogel 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.53 No.3
In this paper, we report an approach based on three-dimensional numerical simulations for the investigation of the dependence of the on/off current ratio in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional and three-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L and thickness t but varying the channel width W from 5 nm and 5 μm. By evaluating the charge distributions and the current flowlines of both the two- and three-dimensional structures, we have shown that the increase in the `on state' conduction current in the SiNW channel is a dominant factor, which consequently results in more than a two order of magnitude improvement in the on/off current ratio. In this paper, we report an approach based on three-dimensional numerical simulations for the investigation of the dependence of the on/off current ratio in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional and three-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L and thickness t but varying the channel width W from 5 nm and 5 μm. By evaluating the charge distributions and the current flowlines of both the two- and three-dimensional structures, we have shown that the increase in the `on state' conduction current in the SiNW channel is a dominant factor, which consequently results in more than a two order of magnitude improvement in the on/off current ratio.
Selective Epitaxial Growth Properties and Strain Characterization of Si1−xGex in SiO2 Trench Arrays
구상모,장현철,고대홍 한국물리학회 2017 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.70 No.7
In this study, we investigated the formation of a Si1−xGex fin structure in SiO2 trench arrays via an ultra-high-vacuum chemical-vapor deposition (UHV-CVD) selective epitaxial growth (SEG) process. Defect generation and microstructures of Si1−xGex fin structures with different Ge concentrations (x = 0.2, 0.3 and 0.45) were examined. In addition, the strain evolution of a Si1−xGex fin structure was analyzed by using reciprocal space mapping (RSM). An (111) facet was formed from the Si1−xGex epi-layer and SiO2 trench wall interface to minimize the interface and the surface energy. The Si1−xGex fin structures were fully relaxed along the direction perpendicular to the trenches regardless of the Ge concentration. On the other hand, the fin structures were fully or partially strained along the direction parallel to the trenches depending on the Ge concentration: fully strained Si0.8Ge0.2 and Si0.7Ge0.3, and a Si0.55Ge0.45 strain-relaxed buffer. We further confirmed that the strain on the Si1−xGex fin structures remained stable after oxide removal and H2/N2 post-annealing.
산소 후열처리가 Ga2O3/4H-SiC 이종접합 다이오드의 온도에 따른 전기적 특성에 미치는 영향 분석
구상모,정승환,이형진,이희재,변동욱 한국반도체디스플레이기술학회 2022 반도체디스플레이기술학회지 Vol.21 No.4
We analyzed the influence of post-annealing on Ga2O3/n-type 4H-SiC heterojunction diode. Gallium oxide (Ga2O3) thin films were deposited by radio frequency (RF) sputtering. Post-deposition annealing at 950℃ in an Oxygen atmosphere was performed. The material properties of Ga2O3 and the electrical properties of the diodes were investigated. Atomic Force Microscopy (AFM), X-Ray Diffraction and Scanning Electron Microscope (SEM) images show a significant increase in the roughness and crystallinity of the O2-annealed films. After Oxygen annealing X-ray Photoelectron Spectroscopy (XPS) shows that the atomic ratio of oxygen increases which is related to a decrease in oxygen vacancy within the Ga2O3 film. The O2-annealed diodes exhibited higher on-current and lower leakage current. Moreover, the ideality factor, barrier height, and thermal activation energy were derived from the current-voltage curve by increasing the temperature from 298 – 434K.
어닐링이 RF 스퍼터링으로 제작된 Ga2O3/Al¬2O3/SiC 소자에 미치는 영향 연구
구상모,이희재,김민영,문수영,변동욱,정승우 한국반도체디스플레이기술학회 2022 반도체디스플레이기술학회지 Vol.21 No.2
We reported on annealing effect on Ga2O3/Al2O3/SiC devices grown by radio frequency sputtering method. Post-deposition annealing at 900 °C was performed, which results in crystallization in the Ga2O3 films. The major peaks (-401) and (403) of Ga2O3 which was thermally treated at 900 °C appears in the x-ray diffraction (XRD) results. Auger electron spectroscopy (AES) shows that Ga and Al atoms seems to be diffused into the opposite direction Al2O3 and Ga2O3 after annealing. Transfer and output characteristics of back-gate transistor were analyzed where SiC substrate is used as gate material. On-state current and on/off ratio increased almost 109 and 106 times higher in the 900 °C annealed sample.