SOI 기판에 형성된 MOSFET의 특성 연구

한명석,이찬희,홍신남 한국항공대학교 1995 論文集 Vol.33 No.-

Thin film SOI 소자는 short channel effect 감소, subthreshold slop의 개선, 높은 이동도, 낮은 기생 캐패시터, latch-up현상이 없는 등의 여러가지 장점들을 가지고 있다. 이것이 ULSI에 대해 실현 가능한 기술이 된 것은 최근에 발달된 양질의 thin film SOI 기관 제작기술에 기인한 것이다. 그렇지만 current kink와 early breakdown 같은 floating body effect와 source/drain 저항의 증가라는 두가지의 큰 문제점을 가지고 있다. 본 연구에서는 concave 구조를 가지는 SOI MOSFET 형태를 통해 문제를 풀어보고자 하였다. 제안된 concave SOI 구조는 항복전압을 높이고 드레인 영역에서의 전계를 감소시켜 kink 현상의 원인이 되는 impact ionization이 발생할 확률을 줄이는 결과를 얻을 수 있었다. Thin-film SOR(Silicon-On-Insulator) devices offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, low parasitic capacitance, latch-up free natere, and so on. This is available technology for ULSI due to recent advances in high quality thin film SOI process technology. However, Thin film SOI devices have several problems-floating body effects, current kink, early breakdown effects, increase in parasitic source/drain resistances. In this paper, a SOI MOSFET with concave structure is analyzed for a sub-half micron regime to solve the above problems. Proposed concave SOI structure showed the increased breakdown voltage and the decreased impact ionization due to the lower electric field near the drain region.

??과 ?? 先非晶質化를 利用하여 形成한 薄膜 接合의 比較

韓明錫,洪信男 한국항공대학교 1991 論文集 Vol.29 No.-

Shallow ?? 접합 형성을 위해 주입에너지가 각각 50keV인 Ge과 As 이온을 이용하여 선비정질화하였다. Doping을 위해 10keV B, 50keV BF₂8keV BF₂이온을 ??의 dose로 주입하였다. 선비정질화 하지않는 single crystal silicon에도 B과 BF₂를 같은 조건로 주입하여 선비정질화된 시편과 재료적, 전기적 특성을 비교 분석하였다. Boron을 10keV 주입한 경우에는 선비정질화 이온의 종류에 관계없이 비슷한 boron SIMS profile을 보이고 있으나, ASR측정에 의한 boron 이온 분포에서는 Ge으로 선비정질화한 경우가 가장 shallow한 접합 깊이를 나타냈다. Sheet 저항 측정 결과에 의하면 Ge으로 선비정질화한 경우가 As으로 선비정질화한 경우보다 더 작게 나타났으며, 다이오드 누설 전류 측정은 선비정질화한 경우보다 더 작게 나타났으며, 다이오드 누설 전류 측정은 선비정질화한 경우나 선비정질화하지 않은 경우 모두 양호한 결과를 보이고 있다. 이온 주입 에너지를 25keV로 낮추어 선비정질화한 경우에는 8keV BF₂이온을 주입하였는데, ASR로 측정한 경우에는 As으로 선비정질화한 경우가 가장 shallow 하였다. 그러나 As으로 선비정질화한 시편은 매우 높은 Rs값과 나쁜 누설 전류 특성을 보여 shallow ??접합 형성을 위해 저에너지 BF₂이온을 주입할 경우에는 As을 사용하는 것보다 Ge을 이용하여 선비정질화 하는 것이 유리함을 알 수 있었다. To form shallow ?? -n junctions, Ge and As ions with 50 and 25keV implantation energies were used for preamorphization. Subsequent 10keV B, 50keV BF₂or 8keV BF₂ion implantation was carried out at a dose of ??. Same B and BF₂ion implantations were performed into single crystalline silicon to compare the material and electrical characteristics with the preamorphized samples. SIMS measurements for 10keV B implanted samples revealed the similar boron distribution for two preamorphized cases, but the ASR profiles indicated that the shallower junctions could be formed by Ge preamorphization. Sheet resistance of Ge preamorphized sample was lower than the As preamorphized sample, and the diode leakage current characteristics were similar for the preamorphized and non-preamorphized samples. For the samples implanted with BF₂ions into the substrates preamorphized with 25keV Ge or As ions, the junction depth measured by ASR was shallowest for the As preamorphized sample among the three implantation conditions. Since very high sheet resistance and leaky diode characteristics were obtained for the samples preamorphized with As ions, Ge preamorphization method is found to be more useful for the purpose of forming shallow ?? junctions using low energy BF₂implantation.

0.5 keV 보론 이온 注入法으로 製造한 p-n 接合 다이오드의 特性 分析

洪信男 한국항공대학교 1990 論文集 Vol.28 No.-

Ultra shallow gated diodes have been fabricated using 500 eV B ion implantation into Ge preamorphized and crystalline silicon substrates. Junction depths following rapid thermal annealing (RTA) for 10 s at 950℃ or 1050℃ were determined to be 60-80nm. These are the shallowest junctions formed via ion implantation reported in the literature. Consideration of several parameters, e.g., reduced B? channeling, increased activation, and reduced junction leakage current, leads to the selection of 15 ke V as the optimal Ge preamorphization energy. Transmission electron microscope results indicated that an 850℃/10s RTA was sufficient to remove the majority of bulk defects resulting from the Ge implant. Resulting reverse leakage currents were as low as 1 nA/㎠ for the 60nm junctions and diode ideality factors ranged from 1.02 to 1.12. Even at RTA temperatures as low as 850℃, the leakage current was only 11nA/㎠.

Investigation of the Ru-Zr Metal Alloy for Use as a Gate Electrode in NMOS Devices

홍신남,박종면 한국물리학회 2010 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.56 No.5

We investigated the applicability of the co-sputtered Ru-Zr alloy metal for use as a gate electrode by fabricating metal oxide semiconductor (MOS) capacitors with Ru-Zr gates. Capacitance-voltage (C-V) measurements were performed on the MOS capacitors, and the effective oxide thickness (EOT) and the flat-band voltage (VFB) were extracted from the measured C-V curves. The flatband voltage varied with the composition of Ru and Zr. The accumulation capacitance and the flat-band voltage did not change much after the annealing. Since the Ru₁Zr₁ alloy was found to have a flat-band voltage suitable for n-channel MOS (NMOS) applications and to exhibit good thermal stability and low sheet resistance, it can be used as a NMOS gate electrode.

RTA와 FA에 모두 적용 가능한 붕소 확산 시뮬레이터의 제작

김재영,홍신남 한국항공대학교 1997 論文集 Vol.35 No.-

실리콘 내에서 붕소의 확산을 시뮬레이션할 수 있는 새로운 시뮬레이터를 설계한다. 이 시뮬레이터는 특히 이온 주입 후의 열처리 공정에 유용하다. 확산에 사용된 모델은 비평형 상태의 확산, 점결함, 점결함-불순물 쌍과 그것들의 대전된 종류, 붕소의 침전 현상에 의한 불순물의 비활성화 등을 모두 고려하였다. 이 시뮬레이터는 납득할 만한 계수들을 이용하여 평형 상태 확산 조건 뿐만이 아니라 비평형 상태에서 이온 주입 후의 확산까지도 적용이 가능하다. 초기 조건과 경계 조건을 이용하여 전체 확산 방정식을 성공적으로 풀 수 있었다. A new simulator is designed for boron diffusion in silicon, which is especially useful for analyzing the annealing process subsequent to ion implantation. The model which is used in this simulator takes into account nonequilibrium diffusion and reactions of point defects and defect-dopant pairs, considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using a resonable parameter values, the simulator covers not only the equilibrium diffusion conditions, but also the nonequilibrium post-implantation diffusion. Using initial conditions and boundary conditions, coupled diffusion equation is solved successfully.

이온주입 및 열처리 조건에 따른 박막접합의 특성 비교

홍신남,김재영 대한전자공학회 1998 電子工學會論文誌, D Vol.d35 No.7

To form 0.2 .mu.m p$^{+}$-n junctions, BF$_{2}$ ions with the energy of 20keV and the dose of 2*10$^{15}$ cm$^{-2}$ were implanted into the crystalline and preamorphized silicon substrates. Th epreamorphization was performed using 45keV, 3*10$^{14}$ cm$^{-2}$ As or Ge ions. Th efurnace annealing and rapid thermal annealing were empolyed to annihilate the implanted damage and to activate the implanted boron ions.The junction properties were analyzed with the measured values of the junction depth, sheet resistances, residual defects, and leakage currents. The thermal cycle of furnace annela followed by rapid thermal annela shows better characteristics than the annealing sequence of rapid thermal anneal and furnace annela.Among the premorphization species, Ge ion exhibited the better characteristics than the As ion.n.

열처리 방법에 따른 접합특성에 관한 연구

한명석,이병학,홍신남 한국항공대학교 1995 論文集 Vol.33 No.-

0.2㎛ 이하의 shallow pㆍ-ⁿ 접합을 형성하기 위하여 주입 에너지가 45KeV 인 As이온과 Ge이온으로 섬비정질화하였고, dopant로는 BF₂ 이논을 24keV로 주입하였으며 dose는 2×10?cm?이다. 열처리 조건은 FA 850℃/min, RTA 1000℃/10sec, RTA 1000℃/10sec와 FA 850℃/min, FA 850℃/40min와 RTA 1000℃/10sec이었다. 또한 RTA의 온도 변화를 주어 FA와의 혼합 열처리를 시뮬레이션한 결과로 RTA의 온도가 FA보다 높은경우에 FA+RTA가 RTA+RA보다 접합깊이가 면저항에서 유리한 특성을 나타내고 있음을 알 수 있었다. 실험결과에서도 시뮬레이션 결과와 동일하게 선비정질화를 이용한 shallow접합의 형성시 Ge으로 선비정질화한 후 FA+RTA의 열처리가 RTA+FA보다 이온 주입후의 결정결함의 제거에 의해 접합깊이와 면저항의 특성이 우수함을 알 수 있었다. To form sub 0.2㎛ ?? junctions, As and Ge ions of 45keV implatation energy were used for preamorphization and BF₂ was used as dopant ion with 25keV implantation energy and the dose of ??. annealing was carried out in the manner of FA 850℃/40min, RTA 1000℃/10sec plus FA 850℃/40min and FA 850℃40min plus RTA 1000℃/sec. Also simulation was performed when the samples were annealed with FA plus the various temperatures of RTA. In respect of junction depth and sheet resistance, FA+RTA was better than RTA+FA, when the temperature of RTA was larger than FA. Tp Form shallow ?? junction, FA+RTA annealing method with GE ion preamorphization showed better junction characteristics than RTA+FA fir junction depth and sheet resiatance via point-defect removal.

자체정열 방법을 이용한 GR(Gate-Recessed) SOI

이충근,한명석,홍신남 한국항공대학교 1997 論文集 Vol.35 No.-

SOI(Silicon-On-Insulator)소자는 집적도의 향상, 단채널 효과의 감소, 임계전압 이하에서 기울기 향상, 높은 이동도, latch-up 제거 등의 우수한 이점을 제공한다. 그러나 SOI소자는 current kink와 early breakdown과 같은 floating-body effect를 나타낸다. Floating-body effect를 줄이기 위해 fully depleted SOI를 사용해야 하나 면저항이 크기 때문에 GR(gate-recessed) SOI가 제안되었다. GR SOI는 floating-body effect와 면저항을 줄일 수 있지만 공정상 복잡성이 따른다. 이 논문에서는 self-alignment method를 이용한 GR SOI 를 제안하여 이러한 문제를 해결하였다. 제안되 구조를 시뮬레이션한 결과 드레인 전류의 크기 향상, floating-body effect제거를 위한 imapct-ionization current를 감소시킬 수 있었다. SOI(Silicon-On-Insulator) devices offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature and so on. But these devices have two problems; floating-body effect causing current kink and early breakdown effect. Fully depleted SOI reduces floating-body effect, but it increases sheet resistances. So gate-recessed SOI is proposed. Gate-recessed SOI can reduce sheet resistance and floating-body effect, but is processing step are complicated. In this paper, gate-recessed SOI using selt-alignment method is proposed to solve the above problems. Proposed structure improved drain current level, decreased sheep resistances of sourcd/drain regions and impact ionization current for removal floating-body effect

MOS Characteristics of Ta-Mo Alloy Electrodes on a ZrO2 Gate Dielectric

홍신남,손기민,안재홍,강영섭 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.53 No.2

Metal-oxide-semiconductor (MOS) capacitors were fabricated to reveal the electrical and the chemical properties of Ta-Mo alloy gate electrodes on ZrO2. The work function of the alloy varied between 4.1 eV and 4.7 eV as the co-sputtering powers of Ta and Mo were changed. Good thermal stability up to 800 ℃ was observed for the alloy with a 90.2 % Ta atomic composition and the extracted work function was 4.1 eV, which is compatible with NMOS applications, but the pure Ta gate electrode exhibited very poor thermal stability; the equivalent oxide thickness (EOT) of the tantalum-gated MOS capacitor decreased drastically after 600 ℃ annealing. The barrier heights between the alloy electrode and the gate dielectric were calculated using a Fowler-Nordheim analysis. Based on the experimental results, the metal alloy with about 90 % Ta and 10 % Mo may be an excellent gate electrode on ZrO2 for NMOS devices.

서울지역 정보사회 촉진을 위한 전기통신 중 , 장기 계획 연구

홍신남 한국통신학회 1991 한국통신학회 전기통신학술연구과제 Vol.- No.-