Mapping of sentinel lymph nodes by firefly fluorescence imaging with da Vinci xi system for endometrial and cervical cancers

( Ji Y Tak ),( Gun O Chong ),( Yoon H Lee ),( Dae G Hong ),( Yoon S Lee ) 대한산부인과학회 2016 대한산부인과학회 학술대회 Vol.102 No.-

Objectives: We evaluate the detection rate and metastasis of primary sentinel nodes (SLN) and downstream secondary fluorescence nodes for endometrial and cervical cancer by firefly fluorescence imaging with da Vinci xi system. Materials and Methods; A total of 27 patients were included in the study (13 endometrial and 14 cervical cancers). Mean age was 55 years (range, 32-73 years). Mean BMI was 25.5 kg/m² (range, 21-39 kg/m²). All patients had inframesenteric paraaortic lymphadenectomy but 11 patients had infrarenal paraaortic lymphadenectomy. All procedures were performed by firefly fluorescence imaging with da Vinci xi system. Four intracervical injection of indocyanine green (ICG) at 3 and 9 o'clock was performed in all cases before insertion of telescope. Results: Total obtained nodes count were 43.4 (range 18-61). Five patients had node metastasis with sentinel node. The mean primary SLN counts were 9.9 (range, 2-15). And downstream 2ndary fluorescent staining nodes count were 14.9 (range, 0-25). And primary SLN was identified in 27 cases (100%), with bilateral pelvic mapping in 25 (93%). An aortic 2ndary SLN was identified in 20 (74%) of the 27 mapped cases as not primary but 2ndary fluorescent nodes. The most frequent site of primary SLN was obturator nodes, external iliac medial node, presacral nodes, internal iliac node, parametrial nodes, and external iliac lateral nodes in the order. And frequent site of downstream 2ndary fluorescent staining node was external iliac lateral nodes, inframesenteric nodes, right paraaortic nodes, external iliac medial nodes, common iliac nodes, presacral nodes, aortocaval node, internal iliac nodes, gluteal node and infrarenal nodes in the order. Positive SLNs were identified in 19% of patients (5/27). Four had secondary paraaortic node metastasis both in patients with positive pelvic SLN. Three patients (11%) had metastatic node outside to metastatic primary SLN and downstream fluorescence nodes (3/27). There were no allergic reactions to the ICG. Conclusions: Firefly fluorescence imaging with ICG in da Vinci system is an excellent and safe method for SLN mapping with a very high overall (100%) and bilateral (93%) detection rate. Our results revealed there are important information about conception of primary sentinel node and downstream fluorescence nodes. Which is rather different results to previous others studies.

축산물 HACCP교육 훈련 효율화 방안

홍종해 ( Chong Hae Hong ),권오건 ( O Gun Kwon ) 한국예방수의학회(구 한국수의공중보건학회) 2011 예방수의학회지 Vol.35 No.3

The Hazard Analysis and Critical Control Points (HACCP) training is a basic element for a successful HACCP implementation in food industry. To train the HACCP professionals, nine training institutes are designated as a HACCP training center in Korea. We analyzed current HACCP training program and its management system, and suggest some points to be made up for more advanced effects of training. These include: (1) development of specified courses and contents to step up the level of HACCP operating and inspecting skills, (2) development and use of standardized teaching materials among institutes, (3) appointment of full-time lecturer to training institutes, (4) buildup of practical exercise in all HACCP courses, (5) nationwide distribution of training institutes.

Adenomyomatous polyp of uterus in Peutz-Jeghers syndrome(초)

배지혜 ( Ji H. Bae ),( Gun O. Chong ),( Won J. Seong ),( Dae G. Hong ),( Young L. Cho ),( Il S. Park ),( Yoon S. Lee ) 대한산부인과학회 2009 대한산부인과학회 학술대회 Vol.95 No.-

Uterine pseudoaneurysm after dilataion & curettage of Hydatidiform mole patient: A case(초)

최민혜 ( Min H. Choi ),( Gun O. Chong ),( Won J Seong ),( Dae G. Hong ),( Young L. Cho ),( Il S. Park ),( Yoon S. Lee ) 대한산부인과학회 2009 대한산부인과학회 학술대회 Vol.95 No.-

DTV 튜너를 위한 CMOS Fractional-N 주파수합성기

고승오(Ko, Seung-O),서희택(Seo, Hee-Teak),박종태(Park, Jong-Tae),유종근(Yu, Chong-Gun) 한국전기전자학회 2010 전기전자학회논문지 Vol.14 No.1

최근 TV 방송의 새로운 시장인 DTV 시장이 넓어지면서 DTV 튜너에 대한 요구도 많아지고 있다. DTV 튜너를 설계하는 데에는 많은 어려운 부분이 있지만, 가장 어려운 부분 중에 하나가 주파수합성기이다. 본 논문에서는 DTV 튜너를 위한 주파수합성기 회로를 CMOS 공정을 사용하여 설계하였다. 설계한 주파수합성기는 DTV(ATSC)의 주파수 대역(54~806MHz)을 만족한다. 하나의 VCO를 사용하여 광대역을 만족시킬 수 있는 구조를 제안하고, LO pulling 효과를 최소화 하기위하여 1.6~3.6GHz 대역에서 동작하도록 설계하였다. 또한 고주파 대역과 저주파 대역에서의 VCO 이득의 차이와 주파수 간격의 변화를 줄여 안정적인 광대역 특성을 구현하였다. 모의실험 결과, 설계한 VCO의 이득은 59~94MHz(17.7MHz/V,23%)이고, 주파수 간격은 26~42.5MHz (8.25MHz/V,24%)이며, tuning range는 76.9%이다. 설계된 주파수합성기의 위상잡음은 100kHz offset에서 -106dBc/Hz이고, 고착시간은 약 정도이다. 설계된 회로는 1.8V 전원전압에서 20~23mA의 전류를 소모하며 칩 면적은 PAD를 포함하여 2.0mm×1.8mm이다. The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(17.7MHz/V,23%) and frequency steps of 26~42.5MHz(8.25MHz/V,24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm×1.8mm.

Laparoscopic pelvic floor repair

이현정 ( Hyun J. Lee ),( Gun O. Chong ),( Yoon S. Lee ) 대한산부인과학회 2004 대한산부인과학회 학술대회 Vol.90 No.-

DTV 튜너를 위한 48MHz~1675MHz 주파수합성기 설계

고승오,서희택,권덕기,유종근,Ko, Seung-O,Seo, Hee-Teak,Kwon, Duck-Ki,Yu, Chong-Gun 한국정보통신학회 2011 한국정보통신학회논문지 Vol.15 No.5

본 논문에서는 DTV 응용을 위한 광대역 주파수 합성기 회로를 $0.18{\mu}m$ CMOS 공정을 사용하여 설계하였다. 설계한 주파수 합성기는 DTV의 모든 주파수 대역을(48MHz~1675MHz) 만족한다. 하나의 VCO만을 사용하여 광대역을 만족시킬 수 있는 구조를 제안하였으며, 고주파 대역과 저주파 대역에서의 VCO 이득의 차이와 주파수 간격의 변화를 줄여 안정적인 광대역 특성을 구현하였다. 모의실험 결과, VCO의 발진주파수 범위는 1.85GHz~4.22GHz이며, 4.2GHz에서 위상잡음은 100kHz offset에서 -89.7dBc/Hz이다. VCO 이득은 62.4~95.8MHz/V(${\pm}21.0%$)이고 주파수 간격은 22.9~47.9MHz(${\pm}35.3%$)이다. 설계된 주파수합성기의 고착시간은 약 $0.15{\mu}s$이다. 제작된 칩을 측정한 결과 VCO는 2.05~3.4GHz의 대역에서 발진하는 것을 확인하였다. 설계된 주파수 보다 shift down 되었지만 마진을 두어서 설계를 하였기 때문에 DTV 튜너로 사용할 수 있는 주파수 대역은 만족한다. 설계된 회로는 1.8V 전원 전압에서 23~27mA의 전류를 소모한다. 칩 면적은 PAD를 포함하여 $2.0mm{\times}1.5mm$이다. In this paper a wideband frequency synthesizer is designed for DTV tuners using a $0.18{\mu}m$ CMOS process. It satisfies the DTV frequency band(48~1675MHz). A scheme is proposed to cover the full band using only one VCO and reliable broadband characteristics are achieved by reducing the variations of VCO gains and frequency steps. The simulation results show that the designed VCO has frequency range of 1.85~4.22GHz, phase noise at 4.22GHz of -89.7dBc/Hz@100kHz, gains of 62.4~95.8MHz/V(${\pm}21.0%$) and frequency steps of 22.9~47.9MHz(${\pm}35.3%$). The designed VCO has a phase noise of -89.75dBc/Hz at 100kHz offset. The designed synthesizer has a lock time less than $0.15{\mu}s$. The measured VCO tuning range is 2.05~3.4GHz. The frequency range is shifted down but still satisfy the target range owing to the design for enough margin. The designed circuit consumes 23~27mA from a 1.8V supply, and the chip size including PADs is $2.0mm{\times}1.5mm$.

Quarter-Rate Bang-Bang 위상검출기를 사용한 0.18㎛ CMOS 10Gbps CDR 회로 설계

차충현(Cha, Chung-Hyeon),고승오(Ko, Seung-O),서희택(Seo, Hee-Taek),박종태(Park, Jong-Tae),유종근(Yu, Chong-Gun) 한국전기전자학회 2009 전기전자학회논문지 Vol.13 No.2

통신시스템에서 데이터 전송이 고속으로 이루어지면서, 하드웨어의 복잡성, 전력소모, 가격 등의 이유로 클럭을 제외한 데이터만 수신단으로 보내는 방식이 사용되어지고 있다. 따라서, 고속으로 수신된 데이터에서 클럭 신호를 추출하는 것이 필요하며, 추출된 클럭을 이용하여 데이터를 복원하는 클럭/데이터 복원회로(CDR)에 관한 연구가 활발히 이루어지고 있다. 본 논문에서는 0.18um CMOS 공정을 이용하여 10Gbps CDR 회로를 설계하였다. 전력소모와 회로의 복잡도를 줄이기 위해 quarter-rate bang-bang 유형의 위상 검출기를 사용하였으며, 지터 특성 향상을 위해 LC 유형의 4단 VCO를 사용하였다. 모의실험 결과, 설계된 CDR 회로는 1.8V 전원전압에서 80mW의 전력을 소모하며, 2.2ps,pp의 클럭 지터 특성을 보인다. 패드를 제외한 칩 레이아웃 면적은 1.26mm×1.05mm이다. With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm×1.05mm.