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RISS 인기검색어
- 검색키워드
- 저자 : Yearn-Ik (검색결과 116 건)
- 무료
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실리콘의 비등방성 부식공정에 대한 Computer Simulation
최연익,문일호 亞洲大學校 1989 論文集 Vol.12 No.-
A Simulation program for the U-groove etching of the silicon has developed on the Hewlett-Packard 9000 desktop computer. The etched patterns for the given rectangular mask patterns were successfully simulated by changing the misorientation angle and/or etch time. When comparing computer results with the experimental ones for the misorientation angles of 0˚,20˚,35.3˚,45˚,54.7˚,70˚,and 90˚or etch time of 10min.,20min. and 30min.,the former has shown good agreement with the latter.
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최연익 亞洲大學校 1984 論文集 Vol.7 No.-
A simulation program was developed to calculate electric potential and field in the reversebiased Schottky diode by quasi three-dimensional numerical analysis. Special features of this program are to deal with taper oxide structures and automatic generation of grid numbers for a reverse voltage given. Schottky diodes with the taper angle of 3˚to 90˚were successfully analyzed using this program.
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최연익,임한조,노영화 亞洲大學校 1986 論文集 Vol.9 No.-
Design programs which can be used for the fabrication of high-voltage power MOSFET's have been developed on HP-15C programmable calculator. Also, we proposed a method for finding optimum gate pitch with source pitch given after the specifications of the starting wafer and fabrication process were determined. The method was applied to the cases of using two kinds of epitaxially grown wafers and variations of on-resistance were studied in terms of source geometry, source pitch, gate-drain over-lap ratio, etc.
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실리콘의 비등방성 부식에 있어서 하부부식에 대한 실험적 고찰
김종오,최연익 亞洲大學校 1987 論文集 Vol.10 No.-
We experimentally studied the undercutting in relation to the misorientatin in the anisotropic etching of the (100) and (110) oriented silicon. The mask patterns were consists of convex(270˚) and concave(90˚) corners or rectangle. The etching has been carried out using a KOH-2-isopropanol-H₂O solution at 80℃. The etch rate was 1.55um/min and 0.85um/min for the (100) and (110) silicon, respectively. In the case of V-groove etching, the undercutting was observed over the whole region except for misorientatin angles(0˚and 90˚) at which the mask pattern parallels {111} planes and only at the convex corner of mask pattern in the case of zero-degree misorientation. In the case of U-groove etching, the undercutting was observed at the convex corner and over the region except for the corners of mask pattern paralleling {111} planes in the case of the misorientation angles(0˚, 35.3˚, 54.7˚ and 90˚) at which the mask pattern parallels {111} planes and over the whole region of make pattern in the other misorientation angles. The proceeding of undercutting in the V-and U -groove etching ends at the horizontal self-stop points(HSSP) which are made by {111} planes without regard to the misorientation. The plane structure of which the final etched pattern is composed of {111} planes is rectangular in the V-groove etching and hexagonal in the U-groove etching regardless of misorientation angle and mask pattern. The ratio of etched depth and width in the final etched pattern was 0.707 and 0.354 in the V-and U-groove etching, respectively.
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김진형,최연익,정상구,박찬광,김충기,성만영 亞洲大學校 1987 論文集 Vol.10 No.-
In this paper, the design of the array type power MOSFETs is discussed in terms of on-resistance, breakdown voltage, placement of FLRs(field limiting ring) and threshold voltage. Also, 9-cell(square-on square grid) VDMOSs are fabricated to confirm the feasibility of the design method. Existence of optimum p-well spacing for minimum on-resistance, which is anticipated by the theoretical results is confirmed by the experiment of the fabricated power MOSFETs. Breakdown voltage of power MOSFET is upgraded by using two FLR's and their optimum placement is determined from the experimental results of the diodes with FLRs. The threshold voltage is controlled by the ion implantation within the design specification. Experimental results are in good agreement with the design specification. Experimental results are in good agreement with the design values. Characteristics of the fabricated power MOSFETs are 190Ω in on-resistance, 270V in breakdown voltage and 2.9V in thershold voltage.
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성만영,최연익 亞洲大學校 1985 論文集 Vol.8 No.-
Optimum design of power MOSFET's has been studied for minimum ON resistance. With the breakdown voltage given, design curves were made to determine thickness and doping concentration of the epitaxial layer for minimum epi resistance. Sensitivity of epi resistance to epi resistivity were studied in practical sense. Concentration of the channel region was calculated for the threshold voltage and gate oxide thickness. From gate-drain overlap ratio at the minimum ON resistance, optimum dimension of s and a was obtained for linear and cell geometry, respectively. A power MOSFET with the breakdown voltage of 350V was designed successfully according to the above-mentioned design procedures.
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Insulated Gate Transistor의 설계 및 제작
정상구,김진형,최연익,이동엽,황성규,성만영 亞洲大學校 1988 論文集 Vol.11 No.-
In this paper, we discuss fabrication and characteristics of the singular and the array-type insulated gate transisters(IGT). The starting wafers were two kinds: for a singular type IGT, p type(100) silicon with n??buffer and n??epitaxial layer; for a array-type IGT, p type(111) silicon with the n??epi layer. The channel regions were defined using the self-aligned double-diffusion process. Aluminum and poly silicon gate were used in the singular and array-type IGT, respectively. Characteristics of the singular IGT shows threshold voltage of 4 V, breakdown voltage of 73V and forward voltage drop of 0.7V. On the whole, the experimental results were in agreement with the theoretical ones when comparing the breakdown voltage and forward voltage drop. On the other hand, array-type IGT shows poor I-V characteristics, relatively low breakdown voltage and large leakage current.
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The Study of Factors that Influence the Surface Electric Field of High Voltage Planar PN Junctions
Park, Yearn-Ik 대한전자공학회 1986 전자공학회논문지 Vol. No.
The effectiveness of field plate and window tapering in reducing the maximum surface electric field of planar pn junctions has been studied by two dimensional computer simulation. The influence of silicon dioxide insulator thickness is also presented.
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