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정재윤(Jae Yun Jung),임홍재(Hong Jae Yim),이상범(Sang Beam Lee),허승진(Seung Jin Heo) 한국자동차공학회 2002 한국자동차공학회 춘 추계 학술대회 논문집 Vol.2002 No.5_2
This paper presents the reliability based design optimization(RBDO) for cantilever beams. We utilized response surface method(RSM) and Monte Carlo simulation to obtain the response surface that describes the limit state function for design constraints of the cantilever beam. Using the RSM and the design optimization technique, we have obtained the optimized section considering the reliability of the cantilever beam.
적응형 보쉬공정(Adaptive Bosch Process)을 이용한 식각된 바닥면 연구
이승용(Seung-Yong Lee),양승국(Seung-Kook Yang),김한형(Han-Hyoung Kim),유한석(Han-Suk Yoo),신상현(Sang-Hyun Sin),장동훈(Dong-Hoon Chang),이일항(El-Hang Lee),오범환(Beam-Hoan O),이승걸(Seung-Gol Lee),박세근(Se-Geun Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
We do not use dedicated Bosch process equipment of high cost, it is uses Bosch process that fit existent ICP(Inductively Coupled Plasma) equipment. Bosch process which is method of deep silicon etching is connected repeatedly in using SF? Plasma for etching process and using C₄F? Plasma the deposition process. However, between etching bottom layer and side wall not verticality and curved layer is formed. It is used about this curved layer phenomenon. because of considering gas fraction, temperature, substrate voltage, process time etc. It is used about this curved layer phenomenon and suggested optimum process condition. Standard process for study of process gas used SF? and Ar, and source power 600W, substrate voltage used -200V. Deposition process used C₄F? gas, and source power 600W, substrate voltage did not used. Process substrate temperature makes via 0℃ and progressed study. Through these processing condition, we manufactured mold for NIL(Nano Imprint Lithography) process.
Choi, Beam-Jin,Lee, Tae-Hong,Lee, Jae-Il,Ko, Jun-Kyeung,Park, Hwa-Seung,Choi, Chang-Hwa The Korean Neurosurgical Society 2011 Journal of Korean neurosurgical society Vol.49 No.3
Objective : Vasospasm of cerebral vessels remains a major source of morbidity and mortality after an aneurysmal subarachnoid hemorrhage (SAH). The purpose of this study was to evaluate the safety and efficacy of transluminal balloon angioplasty (TBA) for SAH-induced vasospasm. Methods : Eleven patients with an angiographically confirmed significant vasospasm (>50% vessel narrowing and clinical deterioration) were studied. A total of 54 vessel segments with significant vasospasm were treated by TBA. Digital subtraction angiography was used to confirm the presence of vasospasm, and TBA was performed to dilate vasospastic arteries. Medical and angiographic reports were reviewed to determine technical efficacy and for procedural complications. Results : TBA using Hyper-Glide or Hyper-Form balloons (MicroTherapeutics, Irvine, CA) was successfully accomplished in 88.9% vasospastic segments (48 of 54), namely, in the distal internal carotid artery (100%, n=7), the middle cerebral artery (100%), including the M1 (n=10), M2 (n=10), and M3 segments (n=4), in the vertebral artery (100%, n=2), basilar artery (100%, n=1), and in the anterior cerebral artery (ACA), including the A1 (66%), A2 (66%), and A3 segments (100%). Vessel diameters significantly increased after TBA. There were no cases of vessel rupture or thromboembolic complications. GCS at one day after TBA showed an improvement in all patients except one. Conclusion : This study suggests that TBA using Hyper-Glide or Hyper-Form balloons is a safe and effective treatment for subarachnoid hemorrhage-induced cerebral vasospasm.
Priming Effect of Rice Seeds on Seedling Establishment under Adverse Soil Conditions
Lee, Suk-Soon,Kim, Jae-Hyeun,Hong, Seung-Beam,Yun, Sang-Hee,Park, Eui-Ho The Korean Society of Crop Science 1998 Korean journal of crop science Vol.43 No.3
An experiment was carried out to find out the priming effects of rice seeds, Oryza sativa L. (cv. Ilpumbyeo) on. the seedling establishment and early emergence under excess soil moisture conditions. Seeds were primed by soaking in -0.6 MPa polyethylene glycol (PEG) solution at $25^{\circ}C$ for 4 days. The primed seeds were sown in soils with various soil moistures (60, 80, 100, 120, and 140% field capacity) at 17 and $25^{\circ}C$, respectively. Germination and emergence rates, plumule height, and radicle length of primed seeds were higher than those of untreated seeds at any soil moisture and temperature examined. The time from planting to 50% germination ($T_{50}$) of primed seeds was less than that of untreated seeds by 0.9~3.7 days. Germination rate, emergence rate, plumule height, and radicle length were highest at the soil moisture of 80% field capacity among the soil moistures. Priming effects of rice seeds on germination and emergence rates were more prominent under the unfavorable soil moistures (60, 100, 120, and 140% field capacity) than those under the optimum soil moisture condition (80% field capacity). However, priming effects on seedling growth were greater at near optimum soil moisture compared with too lower or higher soil moistures. Therefore, these findings suggest that priming of rice seeds may be a useful way for better seedling establishment under the adverse soil conditions.
CMOS 집적회로 테스팅을 위한 내장형 전류 감지 회로 설계
김태상,홍승호,곽철호,김정범,Kim, Tae-Sang,Hong, Seung-Ho,Kwak, Chul-Ho,Kim, Jeong-Beam 한국전기전자학회 2005 전기전자학회논문지 Vol.9 No.1
This paper presents a built-in current sensor(BICS) that detects defects in CMOS integrated circuits using the current testing technique. This circuit employs a cross-coupled connected PMOS transistors, it is used as a current comparator. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT) and high speed detection time. In addition, in the operation of the normal mode, the BlCS does not have dissipation of extra power, and it can be applied to the deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The area overhead of a BlCS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS standard technology. 본 논문에서는 전류 테스팅을 이용하여 CMOS 집적회로에 존재하는 결함을 검출하는 내장형 전류 감지회로를 설계하였다. 이 회로는 일반적인 CMOS 공정으로 구현하였으며 결함전류와 기준전류를 전압으로 변환시켜 시험대상 회로의 결함을 고속으로 검출하며, 미세공정에도 적용가능한 회로이다 제안한 전류 감지회로는 전류원 내장으로 인한 추가적인 전력소모를 문제를 해결하였다. 제안한 회로의 정당성 및 효율성은 HSPICE를 이용한 시뮬레이션으로 그 타당성을 입증하였다. 제안한 전류 감지회로가 칩의 전체 면적에서 차지하는 면적소모는 시험대상회로에서 약 9.2%로, 내장형 전류 감지회로에 의한 면적소모는 무시할 만 하다. 제안한 회로는 Hynix O.35um 2-poly 4-metal N-Well 표준 CMOS 공정으로 제작하였다.