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Design of Pipelined Floating-Point Arithmetic Unit for Mobile 3D Graphics Applications
Choi, Byeong-Yoon,Ha, Chang-Soo,Lee, Jong-Hyoung,Salclc, Zoran,Lee, Duck-Myung Korea Multimedia Society 2008 멀티미디어학회논문지 Vol.11 No.6
In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.