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송낙운 弘益大學校 科學技術硏究所 1993 科學技術硏究論文集 Vol.3 No.-
본 연구에서는 교육용 VHDL 및 관련 CAD 툴을 사용하여 대표적인 디지탈 시스템, 즉, 마이크로프로세서, 디지탈 필터의 설계를 수행한다. VHDL 모의해석의 경우, 행위/구조 모델링을 사용하여 모의해석하였으며, 주어진 입력에 대하여 정상적으로 동작하였으며, 이를 교육용 CAD 툴에 의해 풀커스텀/세미커스텀 설계방식에 의해 레이아웃을 수행하였을때 유사한 결과를 얻을 수가 있었다. 아울러 관련 문제점 및 향후 연구 방향에 관해 논한다. In this work. typical digital systems designs, e.g., microprocessor unit, digital filter, are implemented using education-purpose VHDL and CAD tools. In VHDL simulation, the simulation results using behavioral/structural modeling are performed normally for given inputs and similar results are obtained when layouts are made by full-custom/semi-custom design methods using educational CAD tools. Further, related problems and future research directions are discussed.
宋洛雲,金大硯 弘益大學校 科學技術硏究所 2001 科學技術硏究論文集 Vol.12 No.-
In this paper, the architecture of turbo codec for IMT-2000 system is proposed. The architecture consist of address generator by on-the-fly method and turbo interleaver & encoder using modifed-shift register and memory-saving decoder unusing external RAM. The suggested architecture for turbo codec using in the CDMA2000 standard for IMT-2000 is simulated by C++, VHDL using IDEC C-632 standard cell library. It shows improved coding gain with various code rate & interleaver block size.
송낙운 弘益大學校 科學技術硏究所 1994 科學技術硏究論文集 Vol.5 No.-
In this work, 2D FIR DF is designed and simulated by C. VHDL languages. Designed two-dimensional digital filter mainly consists of one-dimensional digital filter and line memory. Once digital filter coefficients are represented by CSD(Canonical signed Digit) formats, multipliers are realized by hardwired-shifting methods. To speed up the 1D DF block, carry-save adder in each tap and Manchester adder in every 1D DF are adopted. The designed filter is performed up to 30 MHZ and related layouts are now in progress by Berkeley CAD tools.
宋洛雲 弘益大學校 科學技術硏究所 1992 科學技術硏究論文集 Vol.2 No.-
In this work, the VLSI design framework is made by establishing design methodology with respect to the corresponding design levels. To achieve this, the related design CAD softwares, i.e., critical path calculation, schedulingr by simulated annealing, VHDL works, are developed at each design level. The MPC chip is made by the prepared CAD design environment, and presently the data paths such as Booth multiplier, ALU, are designed.
宋洛雲 弘益大學校 1990 弘大論叢 Vol.22 No.2
In this paper, the feasibility of DSP-related IC chip development is studied with respect to world market and technology. It is found that the DSP-related areas, such as HDTV, ISDN, will lead the world semiconductor market in near future. To step up with this fast R&D in this area, it is belived that the top-down design capability, including the cooperation of system designers and semiconductor designers, is obligatory and urgent. Several devices such as codec chips are recommended for development.
송낙운,임윤환 弘益大學校 科學技術硏究所 2000 科學技術硏究論文集 Vol.11 No.-
In this paper, two-dimensional wavelet encoder with efficient architecture for real-time image processing is designed. The architecture consists of parallel filter, input control unit and address control unit, and threee storage module is used to simplify related control units. Further, boundary data unit is made for perfect image decoding and scheduling method is adopted to control restricted hardware efficiently. The designed encoder is simulated by C and VHDL language, where reasonable capability is confirmed.