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New circle clustering algorithm for vehicle routing problem
Jingzhe Li(이경철),Young Hae Lee(이영해),Sonia Irshad Mari(소니아 이르샤드) 한국SCM학회 2015 한국SCM학회지 Vol.15 No.1
Vehicle routing problem has been widely solved by the various algorithms. The sweep algorithm is one of the frequently used algorithms in which the fan-shaped area is calculated after the grouping considering vehicle’s capacity and polar-angle routes in one plane. In this paper, a circle algorithm is proposed which can be used in the particular situations where stops are scattered in a lantern ring area. The proposed circle algorithm considers stops and depot on 2D plane and the plane is divided into ring-shapes with its center of weight. Mathematical models for calculating of vehicle routing distance for both algorithms are derived. Both algorithms are compared based on the derived mathematical models and simulation experiments. The result shows that circle algorithm performs better than sweep algorithm. In order to take advantage of both algorithms, the combined circle and sweep algorithm is suggested for practical use.
HYBRID MEAN VALUE OF THE GENERALIZED KLOOSTERMAN SUMS AND DIRICHLET CHARACTER OF POLYNOMIALS
Jingzhe, Wang Korean Mathematical Society 2013 대한수학회보 Vol.50 No.2
The main purpose of this paper is using the analytic methods and the properties of Gauss sums to study the computational problem of one kind mean value of the generalized Kloosterman sums and Dirichlet character of polynomials, and give an interesting asymptotic formula for it.
RISC 프로세서의 디버거를 위한 변형된 JTAG 설계
허경철(Jingzhe Xu),박형배(Hyungbae Park),정승표(Seungpyo Jung),박주성(Jusung Park) 大韓電子工學會 2011 電子工學會論文誌-SD (Semiconductor and devices) Vol.48 No.7
SoC 설계기술이 발전함에 따라 디버깅이 차지하는 비중은 더욱더 증가되고 있으며 사용자는 빠르고 정확한 디버거를 원하고 있다. 본 논문에서는 새로 설계되는 RISC 프로세서에 적용할 디버거를 위한 변형된 JTAG을 제안 및 설계하여 디버깅 기능 수행에 필요한 사이클을 줄임으로써 빠른 디버거를 구현하였다. 구현된 JTAG은 Core-A의 OCD에 내장하여 SW 디버거와 연동하여 FPGA 레벨까지 검증 마치고 디버거로서의 기능 및 신뢰성을 확인하였다. Core-A의 OCD에 내장된 제안한 JTAG은 기존의 JTAG과 비교하였을 경우, 디버깅 수행 사이클은 수행되는 디버깅 기능에 따라 약 8.5~72.2% 감소되고 추가적으로 게이트 카운트도 약 31.8%감소되었다. As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.
Core-A를 위한 효율적인 On-Chip Debugger 설계 및 검증
허경철(Jingzhe Xu),박형배(Hyungbae Park),정승표(Seungpyo Jung),박주성(Jusung Park) 大韓電子工學會 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.4
최근 SoC 가 주목받으면서 검증이 더욱 중요해졌다. SoC 설계 추세는 구조 및 RTL(Register Transistor Logic) 레벨의 HW(Hardware) 설계 및 내장형 프로세서에서 수행 될 SW(Software) 개발을 동시에 진행하는 HW/SW 통합 설계이다. 테크놀로지가 DSM(Deep-Submicron)으로 가면서 SoC 내부 상태를 확인하는 것은 매우 어려운 일이 되었다. 이와 같은 이유 때문에 SoC 디버거는 매우 어려운 분야이며 디버깅에 매우 많은 시간이 소모된다. 즉 신뢰성이 있는 디버거 개발이 필요하다. 본 논문에서는 JTAG을 기반으로 하는 하드웨어 디버거 OCD를 개발하였다. OCD는 Core-A를 대상으로 하여 개발 된 것이다. 개발된 OCD는 Core-A에 내장하여 SW 디버거와 연동하여 검증까지 마치고 디버거로서의 기능 및 신뢰성을 확인하였다. Core-A에 내장한 OCD는 약 14.7%의 오버헤드를 보이며 OCD의 2% gate count를 차지하는 DCU를 수정함으로써 다른 프로세서에도 쉽게 적용할 수 있는 디버거 유닛으로 사용할 수 있다. Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC’s internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.
Hybrid mean value of the generalized Kloosterman sums and Dirichlet character of polynomials
Wang Jingzhe 대한수학회 2013 대한수학회보 Vol.50 No.2
The main purpose of this paper is using the analytic methods and the properties of Gauss sums to study the computational problem of one kind mean value of the generalized Kloosterman sums and Dirichlet character of polynomials, and give an interesting asymptotic formula for it.
Donghoon Lee,Jingzhe Xu,Jusung Park 대한전자공학회 2010 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
The design and implementation of the digital artificial reverberation system using the floating point Digital Signal Processor is described. For simple and high performance response, Dual All-pass filter (DAPF) is designed. Using DAPFs, a reverberation system has a simpler structure and fewer computations in comparing a commercial system using APFinAPF under a similar condition and both produce similar effect. And a suggested system is implementation to the TI’s floating point DSP. So it works in a real-time.
Design of ISP control system with 32bit RISC processor
Seung-pyo Jung,Jingzhe Xu,Jusung Park 대한전자공학회 2010 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
ISP control system is implemented to two types. The first type which uses OpenRISC 1200 processor to main controller is implemented last year. The second type is implemented with Core-A. The second type is designed to compare Core-A to OpenRISC. Two type ISP control system is tested on FPGA board and checked the core suitability for ISP control system.