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A BIST RAM Architecture With Parallel Testing in a Microprogram ROM
Lai, Feipei,Huang, Jung MEng,Horng, Cheun Jing 대한전자공학회 1991 ICVC : International Conference on VLSI and CAD Vol.2 No.1
Symmetrically simple test patterns for parallel testing of row/column pattern-sensitive faults in RAMS are proposed in the paper. Based on the concept of the maximum leakage current among RAM cells, the worst case testing becomes the critically efficient way of the RAM testing. Due to the simplexity of generating test patterns, we can implement a BIST RAM with test procedures stored in a microprogram ROM to reduce the cost and time of testing. The test complexity of row/column pattern-sensitive faults is reduced to O(N) in an N bits RAM as compared with O(N^(3/2)) of [5].