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Stress grading in integrated power modules
C. Duchesne,M. Mermet-Guyennet,E. Dutarde,T.Lebey,S. Dagdag 전력전자학회 2007 ICPE(ISPE)논문집 Vol.- No.-
Power electronics packaging, like integrated power modules, constitute an advanced technology leading to power density increase, weight and volume decrease and enhancing the reliability level. However, the continuous increase of the voltage lead to questions regarding power device environment. We discuss in the following different solutions able to achieve the electric stress gradation.
Intercollegiate coaches’ experiences with elite international athletes in an American sport context
Catherine Duchesne,Gordon A. Bloom,Catherine M. Sabiston 한국코칭능력개발원 2011 International Journal of Coaching Science Vol.5 No.2
The purpose of this qualitative study was to explore the knowledge and experiences of intercollegiate soccer coaches who have worked with a large number of international athletes. Six head coaches participated in a semi-structured open-ended personal interview. At the time of data collection, each participant was coaching a women’s Division 1 NCAA university soccer team in the United States. Results of the analysis generated knowledge and strategies for coaching culturally diverse athletes and teams. More specifically, all of the coaches appeared to possess a similar level of cultural awareness and understanding which ultimately helped their international athletes’ to grow and develop personally, academically, and athletically.
Chip-underfill Interfaces of Flip Chip Plastic Ball Grid Array Packages
( K. W. Lee ),( M. A. Gaynes ),( E. Duchesne ) 대한금속재료학회 ( 구 대한금속학회 ) 2006 ELECTRONIC MATERIALS LETTERS Vol.2 No.3
High performance electronic packages sometimes fail due to interfacial adhesion degradation during reliability tests. A chip is placed onto a laminate chip carrier in the case of flip chip plastic ball grid array (FC-PBGA) packages. When a flux with pimelic acid is used in a flip chip joining process of a FC-PBGA, it reacts with SnO and SnO2 on chip solder balls or the eutectic paste of the laminate to yield organotin compounds including tin pimelate. There is also minor residue such as tin oxides. The flux residue deposits onto polyimide (PI) which is the passivation layer of integrated circuit chips. In order to improve the reliability of such packages, underfill is introduced into the gap between chip and laminate. The reliability of the underfilled module is tested by subjecting to JEDEC preconditioning at 30 deg.C and 60% relative humidity followed by a solder reflow process at 220-260 deg.C. C-mode scanning acoustic microscopy (CSAM) on such modules shows some delaminated areas at the chip-underfill interface. It is proposed that JEDEC preconditioning of an FC-PBGA package introduces water molecules that accumulate at the flux residue-underfill interface. The interactions between the PI surface and the underfill are broken. Thus, the interface is weakened. Various types of mechanical stresses, which increase during subsequent solder reflow, cause the weakened interfaces to delaminate.