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Memory Design for Artificial Intelligence
Doosan Cho 한국인터넷방송통신학회 2020 International Journal of Internet, Broadcasting an Vol.12 No.1
Artificial intelligence (AI) is software that learns large amounts of data and provides the desired results for certain patterns. In other words, learning a large amount of data is very important, and the role of memory in terms of computing systems is important. Massive data means wider bandwidth, and the design of the memory system that can provide it becomes even more important. Providing wide bandwidth in AI systems is also related to power consumption. AlphaGo, for example, consumes 170 kW of power using 1202 CPUs and 176 GPUs. Since more than 50% of the consumption of memory is usually used by system chips, a lot of investment is being made in memory technology for AI chips. MRAM, PRAM, ReRAM and Hybrid RAM are mainly studied. This study presents various memory technologies that are being studied in artificial intelligence chip design. Especially,MRAM and PRAM are commerciallized for the next generation memory. They have two significant advantages that are ultra low power consumption and nearly zero leakage power. This paper describes a comparative analysis of the four representative new memory technologies.
A Study on Effect of Code Distribution and Data Replication for Multicore Computing Architectures
Doosan Cho 국제문화기술진흥원 2021 International Journal of Advanced Culture Technolo Vol.9 No.4
A multicore system must be able to take full advantage of the program's instruction and data parallelism. This study introduces the data replication technique as a support technique to maximize the program's instruction and data parallelism. Instruction level parallelism can be limited by data dependency. In this case, if data is replicated to each processor core and used, instruction level parallelism can be used to the maximum. The technique proposed in this study can maximize the performance improvement effect when applied to scientific applications such as matrix multiplication operation.
A Case Study of a Navigator Optimization Process
Doosan Cho 한국인터넷방송통신학회 2017 Journal of Advanced Smart Convergence Vol.6 No.1
When mobile navigator device accesses data randomly, the cache memory performance is rapidly deteriorated due to low memory access locality. For instance, GPS (General Positioning System) of navigator program for automobiles or drones, that are currently in common use, uses data from 32 satellites and computes current position of a receiver. This computation of positioning is the major part of GPS which accounts more than 50% computation in the program. In this computation task, the satellite signals are received in real time and stored in buffer memories. At this task, since necessary data cannot be sequentially stored, the data is read and used at random. This data accessing patterns are generated randomly, thus, memory system performance is worse by low data locality. As a result, it is difficult to process data in real time due to low data localization. Improving the low memory access locality inherited on the algorithms of conventional communication applications requires a certain optimization technique to solve this problem. In this study, we try to do optimizations with data and memory to improve the locality problem. In experiment, we show that our case study can improve processing speed of core computation and improve our overall system performance by 14%.
A Study on Efficient Use of Dual Data Memory Banks in Flight Control Computers
Doosan Cho 한국인터넷방송통신학회 2017 International Journal of Internet, Broadcasting an Vol.9 No.1
Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.
Making Utility-Integrated Energy Storage a Used, Useful and Universal Resource
Doosan GridTech Korea Electric Power Corporation 2018 KEPCO Journal on electric power and energy Vol.4 No.1
Objective signs are everywhere that the stationary energy storage market is growing up quickly. The use of distributed resources such as solar photovoltaics and electric vehicles are expanding at a rapid pace, creating technical challenges for the distribution system that will require energy storage and a new generation of software to address. This paper is intended for distribution utility managers and executives and makes the following points: ${\bullet}$ Utility-integrated (as opposed to merely grid-connected) energy storage projects represent a distinct, new wave of industry growth that is just getting underway and is required to manage distributed energy resources moving forward. ${\bullet}$ Utilities and the energy storage industry have important roles to lower risk in adopting this technology - thereby enabling this wave of growth. ${\circ}$ The industry must focus on engineering energy storage for adoption at scale - including the creation and support of software open standards -both to drive down costs and to limit technology and supplier risk for utilities. ${\circ}$ Utilities need to take a program-based, rather than a project- based, approach to this resource to best balance cost and risk as they procure and implement energy storage. By working together to drive down costs and manage risk, utilities and their suppliers can lay the energy storage foundation for a new, more digital distributed electricity system.
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications
Doosan Cho,Pasricha, S.,Issenin, I.,Dutt, N.D.,Minwook Ahn,Yunheung Paek IEEE 2009 IEEE transactions on computer-aided design of inte Vol.28 No.4
<P>Exploiting runtime memory access traces can be a complementary approach to compiler optimizations for the energy reduction in memory hierarchy. This is particularly important for emerging multimedia applications since they usually have input-sensitive runtime behavior which results in dynamic and/or irregular memory access patterns. These types of applications are normally hard to optimize by static compiler optimizations. The reason is that their behavior stays unknown until runtime and may even change during computation. To tackle this problem, we propose an integrated approach of software [compiler and operating system (OS)] and hardware (data access record table) techniques to exploit data reusability of multimedia applications in Multiprocessor Systems on Chip. Guided by compiler analysis for generating scratch pad data layouts and hardware components for tracking dynamic memory accesses, the scratch pad data layout adapts to an input data pattern with the help of a runtime scratch pad memory manager incorporated in the OS. The runtime data placement strategy presented in this paper provides efficient scratch pad utilization for the dynamic applications. The goal is to minimize the amount of accesses to the main memory over the entire runtime of the system, which leads to a reduction in the energy consumption of the system. Our experimental results show that our approach is able to significantly improve the energy consumption of multimedia applications with dynamic memory access behavior over an existing compiler technique and an alternative hardware technique.</P>
조두산(Doosan Cho),정석교(Seokgyo Jung),이주연(Jooyeon Lee),김호균(Hokyun Kim),량영모(Yongmo Liang),백윤흥(Yunheung Paek) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
To achieve high resource utilization for multi-issue DSPs, production compilers commonly include variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The new strategy is referred to as dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP production compiler.