Small-Signal Modeling and Control of Three-Phase Bridge Boost Rectifiers under Non-Sinusoidal Conditions

Chang, Yuan,Jinjun, Liu,Xiaoyu, Wang,Zhaoan, Wang The Korean Institute of Power Electronics 2009 JOURNAL OF POWER ELECTRONICS Vol.9 No.5

This paper proposes a systematic approach to the modeling of the small-signal characteristics of three-phase bridge boost rectifiers under non-sinusoidal conditions. The main obstacle to the conventional synchronous d-q frame modeling approach is that it is unable to identify a steady-state under non-sinusoidal conditions. However, for most applications under non-sinusoidal conditions, the current loops of boost rectifiers are designed to have a bandwidth that is much higher than typical harmonics frequencies in order to achieve good current control for these harmonic components. Therefore a quasi-static method is applied to the proposed modeling approach. The converter small-signal characteristics developed from conventional synchronous frame modeling under different operating points are investigated and a worst case point is then located for the current loop design. Both qualitative and quantitative analyses are presented. It is observed that operating points influence the converter low frequency characteristics but hardly affect the dominant poles. The relationship between power stage parameters, system poles and zeroes is also presented which offers good support for the system design. Both the simulation and experimental results verified the analysis and proposed modeling approach. Finally, the practical case of a parallel active power filter is studied to present the modeling approach and the resultant regulator design procedure. The system performance further verifies the whole analysis.

Transient Characteristics and Physical Constraints of Grid-Tied Virtual Synchronous Machines

Chang Yuan,Chang Liu,Dan Yang,Ruibing Zhou,Niang Tang 전력전자학회 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.4

In modern power systems, distributed generators (DGs) result in high stress on system frequency stability. Apart from the intermittent nature of DGs, most DGs do not contribute inertia or damping to systems. As a result, a new control method referred to as a virtual synchronous machine (VSM) has been proposed, which brought new characteristics to inverters such as synchronous machines (SM). DGs employing an energy storage system (ESS) provide inertia and damping through VSM control. Meanwhile, energy storage presents some physical constraints in the VSM implementation level. In this paper, a VSM mathematical model is built and analyzed. The dynamic responses of the output active power are presented when a step change in the frequency occurs. The influences of the inertia constant, damping factor and operating point on the ESS volume margins are investigated. In addition, physical constraints are proposed based on these analyses. The proposed physical constraints are simulated using PSCAD/EMTDC software and tested through RTDS experiment. Both simulation and RTDS test results verify the analysis.

Comparison of Dynamic Characteristics between Virtual Synchronous Machines Adopting Different Active Power Droop Controls

Chang Yuan,Chang Liu,Xueyin Zhang,Tianyang Zhao,Xiangning Xiao,Niang Tang 전력전자학회 2017 JOURNAL OF POWER ELECTRONICS Vol.17 No.3

In modern power systems, high penetration of distributed generators (DGs) results in high stress on system stability. Apart from the intermittent nature of DGs, most DGs do not contribute inertia or damping to systems. As a result, a new control method named virtual synchronous machine (VSM) was proposed, which brought new characteristics to inverters such as synchronous machines (SMs). In addition, different active power droop controls for VSMs are being proposed in literatures. However, they are quite different in terms of their dynamic characteristics despite of the similar control laws. In this paper, mathematical models of a VSM adopting different active power droop controls are built and analyzed. The dynamic performance of the VSM output active power and virtual rotor angular frequency are presented for different models. The influences of the damping factor and droop coefficient on the VSM dynamic behaviors are also investigated in detail. Finally, the theoretical analysis is verified by simulations and experimental results.

Flyback AC-DC Converter with Low THD Based on Primary-Side Control

Changyuan Chang,Luyang He,Zixuan Cao,Dadi Zhao 전력전자학회 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.6

A single-stage flyback LED AC-DC converter based on primary-side control under constant current mode is proposed in this study. The proposed converter features low total harmonic distortion (THD) and high power factor (PF). It also consists of a zero-crossing distortion compensation circuit and a variable duty ratio control compensation circuit to deal with the line current distortions caused by fixed duty ratio control. The system model and layout are built in Simplis and Cadence, respectively. The feasibility and performance of the proposed circuit is verified by designing and fabricating an IC controller in the HHNEC 0.35 μm 5 V/40 V HVCMOS process. Experimental results show that the PF can reach a level in the range of 0.985–0.9965. Moreover, the average THD of the entire system is approximately 10%, with the minimum being 6.305%, as the input line voltage changes from 85 VAC to 265 VAC.

Design of a High-Precision Constant Current AC-DC Converter with Inductance Compensation

Changyuan Chang,Yang Xu,Bin Bian,Yao Chen,Junjie Hu 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.3

A primary-side regulation AC-DC converter operating in the PFM (Pulse Frequency Modulation) mode with a high precision output current is designed, which applies a novel inductance compensation technique to improve the precision of the output current, which reduces the bad impact of the large tolerance of the transformer primary side inductance in the same batch. In this paper, the output current is regulated by the OSC charging current, which is controlled by a CC (constant current) controller. Meanwhile, for different primary inductors, the inductance compensation module adjusts the OSC charging current finely to improve the accuracy of the output current. The operation principle and design of the CC controller and the inductance compensation module are analyzed and illustrated herein. The control chip is implemented based on a TSMC 0.35μm 5V/40V BCD process, and a 12V/1.1A prototype has been built to verify the proposed control method. The deviation of the output current is within ±3% and the variation of the output current is less than 1% when the inductances of the primary windings vary by 10%.

Analysis and Design of a Separate Sampling Adaptive PID Algorithm for Digital DC-DC Converters

Changyuan Chang,Xin Zhao,Chunxue Xu,Yuanye Li,Cheng`en Wu 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.6

Based on the conventional PID algorithm and the adaptive PID (AD-PID) algorithm, a separate sampling adaptive PID (SSA-PID) algorithm is proposed to improve the transient response of digitally controlled DC-DC converters. The SSA-PID algorithm, which can be divided into an oversampled adaptive P (AD-P) control and an adaptive ID (AD-ID) control, adopts a higher sampling frequency for AD-P control and a conventional sampling frequency for AD-ID control. In addition, it can also adaptively adjust the PID parameters (i.e. Kp, Ki and Kd) based on the system state. Simulation results show that the proposed algorithm has better line transient and load transient responses than the conventional PID and AD-PID algorithms. Compared with the conventional PID and AD-PID algorithms, the experimental results based on a FPGA indicate that the recovery time of the SSA-PID algorithm is reduced by 80% and 67% separately, and that overshoot is decreased by 33% and 12% for a 700㎃ load step. Moreover, the SSA-PID algorithm can achieve zero overshoot during startup.

An Analysis of the Limit Cycle Oscillation in Digital PID Controlled DC-DC Converters

Changyuan Chang,Chao Hong,Xin Zhao,Cheng`en Wu 전력전자학회 2017 JOURNAL OF POWER ELECTRONICS Vol.17 No.3

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.

Rapid Dynamic Response Flyback AC-DC Converter Design

Changyuan Chang,Menglin Wu,Luyang He,Dadi Zhao 전력전자학회 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.6

A constant voltage AC-DC converter based on digital assistant technology is proposed in this paper, which has rapid dynamic response capability. The converter operates in the PFM (Pulse Frequency Modulation) mode. According to the load state, the compensation current produced by the digital compensation module was injected into the CS pin to adjust the switching pulse width dynamically and improve the dynamic response. The control chip is implemented based on NEC 1μm 5V/40V HVCMOS process. A 5V/1.2A prototype has been built to verify the proposed control method. When the load jumps from idle to heavy, the undershoot time is only 7.4ms.

A Novel Zero-Crossing Compensation Scheme for Fixed Off-Time Controlled High Power Factor AC-DC LED Drivers

Changyuan Chang,Hailong Sun,Wenwen Zhu,Yao Chen,Chenhao Wang 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.5

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5㎛ 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

Design of a TRIAC Dimmable LED Driver Chip with a Wide Tuning Range and Two-Stage Uniform Dimming

Changyuan Chang,Zhen Li,Yuanye Li,Chao Hong 전력전자학회 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.2

A TRIAC dimmable LED driver with a wide tuning range and a two-stage uniform dimming scheme is proposed in this paper. To solve the restricted dimming range problem caused by the limited conduction ratio of TRIAC dimmers, a conduction ratio compensation technique is introduced, which can increase the output current up to the rated output current when the TRIAC dimmer turns to the maximum conduction ratio. For further optimization, a two-stage uniform dimming diagram with a rapid dimming curve and a slow dimming curve is designed to make the LED driver regulated visually uniform in the whole adjustable range of the TRIAC dimmer. The proposed control chip is fabricated in a TSMC 0.35μm 5V/650V CMOS/LDMOS process, and verified on a 21V/500mA circuit prototype. The test results show that, in the 90V/60Hz~132V/60Hz ac input range, the voltage linear regulation is 2.6%, the power factor is 99.5% and the efficiency is 83%. Moreover, in the dimming mode, the dimming rate is less than 1% when the maximum dimming current is 516mA and the minimum dimming current is only about 5mA.