http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads
Byungsub Kim,Jae-Yoon Sim,Hong-June Park 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.3
This paper reports an adaptive positive feedback bias control technique for operational transconductance amplifiers to adjust the bias current based on the output current monitored by a current replica circuit. This technique enables operational transconductance amplifiers to quickly adapt their power consumption to various analog workloads when they are configured with negative feedback. To prove the concept, a test voltage follower is fabricated in 0.5-μm CMOS technology. Measurement result shows that the power consumption of the test voltage follower is approximately linearly proportional to the load capacitance, the signal frequency, and the signal amplitude for sinusoidal inputs as well as square pulses.
Different behaviors of half-metallic ferromagnetism of Cr-doped AlN and InN
Kang, ByungSub,Lee, HaengKi,Kim, KyeongSup,Kang, HeeJae Royal Swedish Academy of Sciences 2009 Physica scripta Vol.79 No.2
<P>The electronic structure and magnetism are studied for the zinc-blende and wurtzite (Al,Cr)N, (Ga,Cr)N and (In,Cr)N by using the full potential linear muffin-tin orbital method. The energy gap (quasi-gap) in Cr-doped wurtzite InN decreases exponentially with increasing the Cr concentration from 0.027 to 0.166. The half-metallicity is retained in the whole range of concentrations considered, whereas for (Al,Cr)N, the half-metallic character disappears at a concentration of 0.166. The Cr magnetic moment in AlN is about 2.12–2.40μ<SUB>B</SUB> Cr atom<SUP>−1</SUP> with changing the Cr concentration, and for Cr in InN, it is a nearly constant value of 3.0 μ<SUB>B</SUB> Cr atom<SUP>−1</SUP>.</P>
An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads
Kim, Byungsub,Sim, Jae-Yoon,Park, Hong-June The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.3
This paper reports an adaptive positive feedback bias control technique for operational transconductance amplifiers to adjust the bias current based on the output current monitored by a current replica circuit. This technique enables operational transconductance amplifiers to quickly adapt their power consumption to various analog workloads when they are configured with negative feedback. To prove the concept, a test voltage follower is fabricated in $0.5-{\mu}m$ CMOS technology. Measurement result shows that the power consumption of the test voltage follower is approximately linearly proportional to the load capacitance, the signal frequency, and the signal amplitude for sinusoidal inputs as well as square pulses.
The Oscillation Frequency of CML-based Multipath Ring Oscillators
Sanquan Song,Byungsub Kim,Wei Xiong 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.6
A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor α, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor α an attractive option for lower power applications.
The Oscillation Frequency of CML-based Multipath Ring Oscillators
Song, Sanquan,Kim, Byungsub,Xiong, Wei The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.6
A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor ${\alpha}$, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor ${\alpha}$ an attractive option for lower power applications.
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation
Seon-Kyoo Lee,Byungsub Kim,Hong-June Park,Jae-Yoon Sim IEEE 2013 IEEE journal of solid-state circuits Vol.48 No.9
<P>This paper presents an adaptive far-end crosstalk cancellation scheme for a single-ended parallel receiver. The adaptation engine is embedded in a single representative channel CDR, and the receiver efficiently reduces the crosstalk noise with a minimal cost in hardware and power consumption. In addition, the proposed scheme can be applied to any given CDR and equalizing circuits. The receiver is fabricated in 0.13 μm CMOS technology and achieves a reduction of FEXT-induced jitter up to 75%. The receiver consumes 65 mW at 5 Gb/s (4.3 mW/Gb/s/pin) including a PLL for global clock distribution.</P>
성기환(Kihwan Seong),김병섭(Byungsub Kim),심재윤(Jae-Yoon Sim),박홍준(Hong-June Park) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.6
A multi-phase phase-locked loop (PLL) was implemented for the first time by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was reduced by half by the operation of a coarse phase detector that utilize 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks is measured to be 6ps at 480 MHz. The PLL chip in a 65 nm process occupies 0.038 mm<SUP>2</SUP> , consumes 4.8 mV at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.